What if the Module_instance name starts with this slash "/"

D

dipesh.trivedi

Guest
Dear friends,

I have been working on verilog after a very long time.
i am using $sdf_annotation statement to annotate the *.sdf file.
the statement written by me is as follows,

$sdf_annotate("Top_add.max.sdf", TOPCHIP.\Top_clk_gen/Top_pat_gen);

here "\Top_clk_gen/Top_pat_gen" is the module instance name. But the
compiler is giving error, which is "expecting a right parenthesis
(')')"

How can i write it correctly. Please guide me.

Thanks in advance.

I will be waiting for your advices.

Regards,
Dipesh.
 
dipesh.trivedi wrote:
Dear friends,

I have been working on verilog after a very long time.
i am using $sdf_annotation statement to annotate the *.sdf file.
the statement written by me is as follows,

$sdf_annotate("Top_add.max.sdf", TOPCHIP.\Top_clk_gen/Top_pat_gen);

here "\Top_clk_gen/Top_pat_gen" is the module instance name. But the
compiler is giving error, which is "expecting a right parenthesis
(')')"

How can i write it correctly. Please guide me.

Thanks in advance.

I will be waiting for your advices.

Regards,
Dipesh.
Isn't the \ a literal character? Since you have no space to end the
literal, the "Top_clk_gen/Top_pat_gen);" module is what's being looked
for. I take it this is a flattened design? To keep the flattened
"Top_clk_gen/Top_pat_gen" name, just add a space as a delimiter between
the name and the closing parenthesis. The space is what ends the literal.

It's been a while since I messed with this \slash so I'm happy to be wrong.

- John_H
 
On May 8, 2:03 pm, John_H <newsgr...@johnhandwork.com> wrote:
dipesh.trivedi wrote:
Dear friends,

I have been working on verilog after a very long time.
i am using $sdf_annotation statement to annotate the *.sdf file.
the statement written by me is as follows,

$sdf_annotate("Top_add.max.sdf", TOPCHIP.\Top_clk_gen/Top_pat_gen);

here "\Top_clk_gen/Top_pat_gen" is the module instance name. But the
compiler is giving error, which is "expecting a right parenthesis
(')')"

How can i write it correctly. Please guide me.

Thanks in advance.

I will be waiting for your advices.

Regards,
Dipesh.

Isn't the \ a literal character? Since you have no space to end the
literal, the "Top_clk_gen/Top_pat_gen);" module is what's being looked
for. I take it this is a flattened design? To keep the flattened
"Top_clk_gen/Top_pat_gen" name, just add a space as a delimiter between
the name and the closing parenthesis. The space is what ends the literal.

It's been a while since I messed with this \slash so I'm happy to be wrong.

- John_H
Thank you very much John for your precious advice.
Yes it is a flattened design. It's very first time i am dealing with
flattened design.
It seems its bit difficult to debug netlist.

Anyways thank you very much once again. I appreciate your help.

Regards,
Dipesh.
 
On Wed, 7 May 2008 20:22:50 -0700 (PDT), "dipesh.trivedi"
<dipesh.trivedi@gmail.com> wrote:

Dear friends,

I have been working on verilog after a very long time.
i am using $sdf_annotation statement to annotate the *.sdf file.
the statement written by me is as follows,

$sdf_annotate("Top_add.max.sdf", TOPCHIP.\Top_clk_gen/Top_pat_gen);

here "\Top_clk_gen/Top_pat_gen" is the module instance name. But the
compiler is giving error, which is "expecting a right parenthesis
(')')"

How can i write it correctly. Please guide me.
You are using an "escaped identifier". Your instance name
Top_clk_gen/Top_pat_gen
is, of course, not legal Verilog - so it is escaped with the
backslash.

However, an escaped identifier MUST end with some white space.
So, in fact, your identifier is

Top_clk_gen/Top_pat_gen);

(yes, the parenthesis and semicolon are LEGAL in an escaped
identifier!) and therefore your function call to $sdf_annotate
is illegal. Add a space character after the end of the name,
just before the closing parenthesis:

$sdf_annotate("Top_add.max.sdf",
TOPCHIP.\Top_clk_gen/Top_pat_gen ); // NOTE extra space

and things might start to work.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 

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