D
dipesh.trivedi
Guest
Dear friends,
I have been working on verilog after a very long time.
i am using $sdf_annotation statement to annotate the *.sdf file.
the statement written by me is as follows,
$sdf_annotate("Top_add.max.sdf", TOPCHIP.\Top_clk_gen/Top_pat_gen);
here "\Top_clk_gen/Top_pat_gen" is the module instance name. But the
compiler is giving error, which is "expecting a right parenthesis
(')')"
How can i write it correctly. Please guide me.
Thanks in advance.
I will be waiting for your advices.
Regards,
Dipesh.
I have been working on verilog after a very long time.
i am using $sdf_annotation statement to annotate the *.sdf file.
the statement written by me is as follows,
$sdf_annotate("Top_add.max.sdf", TOPCHIP.\Top_clk_gen/Top_pat_gen);
here "\Top_clk_gen/Top_pat_gen" is the module instance name. But the
compiler is giving error, which is "expecting a right parenthesis
(')')"
How can i write it correctly. Please guide me.
Thanks in advance.
I will be waiting for your advices.
Regards,
Dipesh.