P
Pearls Harbour
Guest
Hi, there:
I need the "delay" to allow run empty for index cycles, then
in each dat_en window, dat is incremented.
Thanks.
module tasks;
reg clk;
reg rst;
reg [7:0] dat;
reg dat_clk;
reg dat_en;
initial
begin
delay(100);
data_in(100);
delay(100);
data_in(100);
delay(100);
data_in(100);
delay(100);
$finish;
end
initial
begin
clk <= 1'b0;
forever begin
#5 clk <= 1'b1;
#5 clk <= 1'b0;
end
end
task delay;
input [31:0] index;
integer i;
begin
for(i = 0; i <= index; i = i + 1) @(posedge clk);
end
endtask
task data_in;
input [31:0] index;
integer i, j;
begin
rst <= 1'b0;
dat <= 8'd01;
dat_en <= 1'b1;
dat_clk <= 1'b1;
@(posedge clk);
rst <= 1'b1;
for(j = 0; j <= index; j = j + 1) begin
for(i = 0; i <= 5; i = i + 1) begin
@(posedge clk);
dat <= dat + 8'd1;
dat_clk <= 1'b1;
@(posedge clk);
dat <= dat + 8'd1;
dat_clk <= 1'b0;
end
end
dat_en <= 1'b0;
@(posedge clk);
rst <= 1'b0;
end
endtask
endmodule
I need the "delay" to allow run empty for index cycles, then
in each dat_en window, dat is incremented.
Thanks.
module tasks;
reg clk;
reg rst;
reg [7:0] dat;
reg dat_clk;
reg dat_en;
initial
begin
delay(100);
data_in(100);
delay(100);
data_in(100);
delay(100);
data_in(100);
delay(100);
$finish;
end
initial
begin
clk <= 1'b0;
forever begin
#5 clk <= 1'b1;
#5 clk <= 1'b0;
end
end
task delay;
input [31:0] index;
integer i;
begin
for(i = 0; i <= index; i = i + 1) @(posedge clk);
end
endtask
task data_in;
input [31:0] index;
integer i, j;
begin
rst <= 1'b0;
dat <= 8'd01;
dat_en <= 1'b1;
dat_clk <= 1'b1;
@(posedge clk);
rst <= 1'b1;
for(j = 0; j <= index; j = j + 1) begin
for(i = 0; i <= 5; i = i + 1) begin
@(posedge clk);
dat <= dat + 8'd1;
dat_clk <= 1'b1;
@(posedge clk);
dat <= dat + 8'd1;
dat_clk <= 1'b0;
end
end
dat_en <= 1'b0;
@(posedge clk);
rst <= 1'b0;
end
endtask
endmodule