What equivalent of reg in Verilog to VHDL

Hi,

I am new to Verilog. I know VHDL variable. When I see reg in Verilog, it looks like VHDL variable. Is it right? Please explain it to me.

Thanks,

 

[GaborSzakacs]

rxjwg98@gmail.com wrote:

Hi,

I am new to Verilog. I know VHDL variable. When I see reg in Verilog, it looks like VHDL variable. Is it right? Please explain it to me.

Thanks,

A reg could be either a variable or a signal depending on
how it's used. From an accessibility standpoint, a reg is
always a signal in that it can be used outside the process
where it is assigned. From the standpoint of taking on
a new value immediately or after the process completes,
it will be like a "variable" when you use the blocking =
assignment, or a "signal" when you use the non-blocking <=
assignment. Note that the fact that it can act like a
variable and a signal at the same time means you can get
in trouble if for example you use blocking = assignment
in a clocked process and then use the same reg in another
clocked process (race condition).

Unlike a signal in VHDL, the reg cannot be used for
direct connection (module ports in instantiation) or
continuous assignment.

The closest thing to a variable in VHDL is a reg defined
inside a named process and assigned using only blocking
assignments.

--
Gabor