F
fl
Guest
Hi,
I see an example on Xilinx FPGA with tool Synplify-Pro:
attribute syn_multstyle : string;
attribute syn_multstyle of MULT : signal is "logic";
I only have Xilinx IDE. How can I get the above constraint in IDE?
I am working on Xilinx Spartan-6.
Thanks,
I see an example on Xilinx FPGA with tool Synplify-Pro:
attribute syn_multstyle : string;
attribute syn_multstyle of MULT : signal is "logic";
I only have Xilinx IDE. How can I get the above constraint in IDE?
I am working on Xilinx Spartan-6.
Thanks,