What does what standard say about this:

[Alvin Andries]

library IEEE;
use IEEE.STD_LOGIC_1164.all;


comp_value : STD_LOGIC_VECTOR(7 downto 0);


if (comp_value < "000000001") then ...


This passed withhout warning through Synopsys DC and Formality.
Unfortunately, they disagree on what should happen.

Things that bother me about this construct:
1) no ARITH loaded, so where is this defined (I've got IEEE access, so the
proper STD should be ok)?
2) different vector lengths, so I expect troubles

The only thing I could deduce from Mentor's Modelsim source files, is that
STD_LOGIC_VECTOR(L) < STD_LOGIC_VECTOR(L) behaves like UNSIGNEDs where in
place.

Kind regards,
Alvin.

 

[Mike Treseler]

Alvin Andries wrote:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

comp_value : STD_LOGIC_VECTOR(7 downto 0);

if (comp_value < "000000001") then ...

This passed withhout warning through Synopsys DC and Formality.
Unfortunately, they disagree on what should happen.

http://groups.google.com/group/comp.lang.vhdl/search?group=comp.lang.vhdl&q=std_logic_vector+implicit+comparison

 

[KJ]

"Alvin Andries" <Alvin_Andries.no_spam@no.spam.versateladsl.be> wrote in
message news:4738bfc0$0$7169$bf4948fe@news.tele2.nl...

library IEEE;
use IEEE.STD_LOGIC_1164.all;


comp_value : STD_LOGIC_VECTOR(7 downto 0);


if (comp_value < "000000001") then ...


This passed withhout warning through Synopsys DC and Formality.
Unfortunately, they disagree on what should happen.

Things that bother me about this construct:
1) no ARITH loaded, so where is this defined (I've got IEEE access, so the
proper STD should be ok)?

The comparison will be made from left to right through the elements of the
vectors, looking at each element individually. So the comparison will work
like this...
1. check for comp_value(7) < '0'
2. if comp_value(7) = '0' then check for comp_value(6) < '0'
3. Keep going until you get to bit 0.

2) different vector lengths, so I expect troubles

You'll get them too, although I forget just what happens if you try to

compare two vectors of different lengths....it's generally a design error
that you fix, not some behaviour that is of any good use in my experience.

The only thing I could deduce from Mentor's Modelsim source files, is that
STD_LOGIC_VECTOR(L) < STD_LOGIC_VECTOR(L) behaves like UNSIGNEDs where in
place.

Comparison of two std_logic_vectors happens without any numerical
interpretation of those vectors, it is simply an element by element
comparison of those vectors. A particular element of an enumerated type is
considered 'less than' some other thing of that same type if it is to the
'left' of the other thing being compared. If you take a look at
std_logic_1164 and look for the actual definition of the std_ulogic type,
you'll see that it is a list of characters. Those are the enumerations,
that's where you'll find the '0', '1', 'X', '-', 'U', etc. In that list,
'0' will be to the left of '1'.

Of course, one can also provide a function override to "<" and make it come
out however you want it to (like in std_logic_arith), but if no such
override is in place the above mentioned behavour is how the language will
interpret it.

Just curious, in what way Synopsys DC and Formality actually disagree?

KJ

 

[Andy]

On Nov 12, 6:15 pm, "KJ" <kkjenni...@sbcglobal.net> wrote:

"Alvin Andries" <Alvin_Andries.no_s...@no.spam.versateladsl.be> wrote in
messagenews:4738bfc0$0$7169$bf4948fe@news.tele2.nl...





library IEEE;
use IEEE.STD_LOGIC_1164.all;

comp_value : STD_LOGIC_VECTOR(7 downto 0);

if (comp_value < "000000001") then ...

This passed withhout warning through Synopsys DC and Formality.
Unfortunately, they disagree on what should happen.

Things that bother me about this construct:
1) no ARITH loaded, so where is this defined (I've got IEEE access, so the
proper STD should be ok)?

The comparison will be made from left to right through the elements of the
vectors, looking at each element individually. So the comparison will work
like this...
1. check for comp_value(7) < '0'
2. if comp_value(7) = '0' then check for comp_value(6) < '0'
3. Keep going until you get to bit 0.

2) different vector lengths, so I expect troubles

You'll get them too, although I forget just what happens if you try to
compare two vectors of different lengths....it's generally a design error
that you fix, not some behaviour that is of any good use in my experience.

The only thing I could deduce from Mentor's Modelsim source files, is that
STD_LOGIC_VECTOR(L) < STD_LOGIC_VECTOR(L) behaves like UNSIGNEDs where in
place.

Comparison of two std_logic_vectors happens without any numerical
interpretation of those vectors, it is simply an element by element
comparison of those vectors. A particular element of an enumerated type is
considered 'less than' some other thing of that same type if it is to the
'left' of the other thing being compared. If you take a look at
std_logic_1164 and look for the actual definition of the std_ulogic type,
you'll see that it is a list of characters. Those are the enumerations,
that's where you'll find the '0', '1', 'X', '-', 'U', etc. In that list,
'0' will be to the left of '1'.

Of course, one can also provide a function override to "<" and make it come
out however you want it to (like in std_logic_arith), but if no such
override is in place the above mentioned behavour is how the language will
interpret it.

Just curious, in what way Synopsys DC and Formality actually disagree?

KJ

KJ is correct about the left to right comparison, but IINM, it is only
for equal length vectors. If the vector lengths are unequal, the
shorter vector is (supposed to be) always less than the longer vector
regardless of the contents of both. When comparing elements in equal
length vectors, the elements are compared per the order of their
appearance in the std_ulogic type definition. I agree that comparison
of unequal length std_logic_vectors is practically useless in
synthesis.

Andy

 

[Jonathan Bromley]

On Tue, 13 Nov 2007 07:06:26 -0800,
Andy <jonesandy@comcast.net> wrote:

KJ is correct about the left to right comparison, but IINM, it is only
for equal length vectors. If the vector lengths are unequal, the
shorter vector is (supposed to be) always less than the longer vector
regardless of the contents of both.

I fear you _are_ mistaken, at least in this small detail...

"Built-in" vector comparison is essentially string
comparison. If you were sorting a bunch of strings into
dictionary order, I'm sure you would agree with VHDL
that all the following relations are true:

"AD" > "AC"
"ABCD" > "AABCD" -- shorter string is "larger"
"AACD" > "AAC"

The same thing happens with std_logic_vector, except
that the collating sequence is determined by the order
of characters' appearance in the std_ulogic enumeration
rather than their alphabetical order:

'U' < 'X' < '0' < '1' < 'W' < 'L' < 'H' < 'Z' < '-'

As others have correctly stated, the only *practical*
use of this is that you can compare two std_logic_vector
provided that...
(1) they are of _equal_length_ and
(2) their vectors contain only '0' and '1' elements

If both these conditions are true, you get unsigned
arithmetic comparison. If not, you get very very silly
behaviour; for example
"11" > "101"
"L" > "1"

Of course, the numeric_std package overloads the comparison
operators so that they work "correctly" (i.e. arithmetically)
for any operand lengths. And, of course, that's the right
way to do it.
--
Jonathan Bromley, Consultant

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