What clock domain is a Xilinx DCM LOCK signal in?

J

John Providenza

Guest
I don't see in the Xilinx documentation in what clock domain
the LOCK signal coming from a DCM is produced. Do I need to
synchronize it into the CLK0 domain to avoid metastability?

Thanks!


John Providenza
 
You can phase align feedback using either the CLK0 or CLK2X DCM outputs.

There is a relatively new application note on DCMs in Spartan-3 that may be
useful to your question.

XAPP462: Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs
http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf

Phase alignment is optional for the Digital Frequency Synthesizer function
in a DCM.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC


"John Providenza" <johnp3+nospam@probo.com> wrote in message
news:349ef8f4.0309101349.2cbe675a@posting.google.com...
I don't see in the Xilinx documentation in what clock domain
the LOCK signal coming from a DCM is produced. Do I need to
synchronize it into the CLK0 domain to avoid metastability?

Thanks!


John Providenza
Click to expand...
 
I understand about the phase align capabilities provided by the DCM,
but what clock domain are the LOCKED and STATUS bits created in?

I want to feed LOCKED into a state machine, but I don't see in the
Xilinx docs anyplace which clock produces it.

John Providenza


"Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:<bjobmb$oab1@cliff.xsj.xilinx.com>...
You can phase align feedback using either the CLK0 or CLK2X DCM outputs.

There is a relatively new application note on DCMs in Spartan-3 that may be
useful to your question.

XAPP462: Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs
http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf

Phase alignment is optional for the Digital Frequency Synthesizer function
in a DCM.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC


"John Providenza" <johnp3+nospam@probo.com> wrote in message
news:349ef8f4.0309101349.2cbe675a@posting.google.com...
I don't see in the Xilinx documentation in what clock domain
the LOCK signal coming from a DCM is produced. Do I need to
synchronize it into the CLK0 domain to avoid metastability?

Thanks!


John Providenza
Click to expand...
 
Everything, except the RESET input, is controlled by the rising edge of
CLKIN.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC

"John Providenza" <johnp3+nospam@probo.com> wrote in message
news:349ef8f4.0309111534.36aadea9@posting.google.com...
I understand about the phase align capabilities provided by the DCM,
but what clock domain are the LOCKED and STATUS bits created in?

I want to feed LOCKED into a state machine, but I don't see in the
Xilinx docs anyplace which clock produces it.

John Providenza


"Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message
news:<bjobmb$oab1@cliff.xsj.xilinx.com>...
You can phase align feedback using either the CLK0 or CLK2X DCM outputs.

There is a relatively new application note on DCMs in Spartan-3 that may
be
useful to your question.

XAPP462: Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs
http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf

Phase alignment is optional for the Digital Frequency Synthesizer
function
in a DCM.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC


"John Providenza" <johnp3+nospam@probo.com> wrote in message
news:349ef8f4.0309101349.2cbe675a@posting.google.com...
I don't see in the Xilinx documentation in what clock domain
the LOCK signal coming from a DCM is produced. Do I need to
synchronize it into the CLK0 domain to avoid metastability?

Thanks!


John Providenza
Click to expand...
 
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