What are the two ':' in a table definition?

[Robert Willy]

Hi,

I see the following in a tutorial example. I don't understand the two ':' in
the example. Other on line tutorial only has one ':' in a table module.





primitive dff (q,clk,d,nrst,nset);
input clk,d,nrst,nset;
output q;
reg q;
//initial
// q = 1'b1;
table
// clk d nrst nset q q+
? ? X ? : ? : X ;
? ? ? X : ? : X ;
? ? 0 1 : ? : 0 ;
? ? 1 0 : ? : 1 ;
? ? 0 0 : ? : X ;
(01) 0 1 1 : ? : 0 ;
(01) 1 1 1 : ? : 1 ;
n ? 1 1 : ? : - ;
? * 1 1 : ? : - ;
//
? ? r 1 : ? : - ;
endtable
endprimitive


Second, it has the comments:

//initial
// q = 1'b1;


but I do not see it is formally to define the initial states. What is the \
purpose of the author?


Thanks,

 

[Robert Willy]

On Saturday, March 14, 2015 at 6:55:30 PM UTC-7, Robert Willy wrote:

Hi,

I see the following in a tutorial example. I don't understand the two ':' in
the example. Other on line tutorial only has one ':' in a table module.





primitive dff (q,clk,d,nrst,nset);
input clk,d,nrst,nset;
output q;
reg q;
//initial
// q = 1'b1;
table
// clk d nrst nset q q+
? ? X ? : ? : X ;
? ? ? X : ? : X ;
? ? 0 1 : ? : 0 ;
? ? 1 0 : ? : 1 ;
? ? 0 0 : ? : X ;
(01) 0 1 1 : ? : 0 ;
(01) 1 1 1 : ? : 1 ;
n ? 1 1 : ? : - ;
? * 1 1 : ? : - ;
//
? ? r 1 : ? : - ;
endtable
endprimitive


Second, it has the comments:

//initial
// q = 1'b1;


but I do not see it is formally to define the initial states. What is the \
purpose of the author?


Thanks,

My guess: the first q is output signal, the fifth column.
The second q+ is the reg, the last column?

The 'q' column is all '?'. It still cannot be omitted? A reg must require a
output signal preceding it? I am new to verilog.

 

[Sharad]

On Sunday, March 15, 2015 at 10:04:10 AM UTC+8, Robert Willy wrote:

On Saturday, March 14, 2015 at 6:55:30 PM UTC-7, Robert Willy wrote:
Hi,

I see the following in a tutorial example. I don't understand the two ':' in
the example. Other on line tutorial only has one ':' in a table module.





primitive dff (q,clk,d,nrst,nset);
input clk,d,nrst,nset;
output q;
reg q;
//initial
// q = 1'b1;
table
// clk d nrst nset q q+
? ? X ? : ? : X ;
? ? ? X : ? : X ;
? ? 0 1 : ? : 0 ;
? ? 1 0 : ? : 1 ;
? ? 0 0 : ? : X ;
(01) 0 1 1 : ? : 0 ;
(01) 1 1 1 : ? : 1 ;
n ? 1 1 : ? : - ;
? * 1 1 : ? : - ;
//
? ? r 1 : ? : - ;
endtable
endprimitive


Second, it has the comments:

//initial
// q = 1'b1;


but I do not see it is formally to define the initial states. What is the \
purpose of the author?


Thanks,

My guess: the first q is output signal, the fifth column.
The second q+ is the reg, the last column?

The 'q' column is all '?'. It still cannot be omitted? A reg must require a
output signal preceding it? I am new to verilog.

Willy,

This table describes a sequential UDP (user defined primitive). The 5th column i.e. q reflects the "current state" and the output while the 6th column i.e 'q+" reflects the next state. The above description is that of a D-FF. The initialization is optional and hence the author commented q = 1'b1. The next state describes the state of D-FF after the clock transition.

Check the following links for more details:
http://verilog.renerta.com/source/vrg00055.htm
http://www.asic-world.com/verilog/udp1.html

Regards,
Sharad