what are the semantics of yosys $alu and $macc cells?

[Johann Klammer]

I'd like to know if I can implement them with single bit full adders
and single bit mult cells only, or if I need additional primitives.

(trying to guess the semantics from the logic ops in their simulation
modules just makes my head hurt)

 

[Johann Klammer]

On 02/29/2016 05:38 PM, Johann Klammer wrote:

I'd like to know if I can implement them with single bit full adders
and single bit mult cells only, or if I need additional primitives.

(trying to guess the semantics from the logic ops in their simulation
modules just makes my head hurt)


and what's those $lcu things (in techmap.v)