What are the preferred Virtex5/Virtex6 configuration methods

[Rich]

Hello all,

In a seperate thread, there was a brief discussion on what features
are needed in a evaluation kit. So related to that, I'm wondering
what is the preferred method out there for configuring Virtex 5 and
Virtex 6 devices. I"m using commodity parallel flash directly
connected to the FPGA. It uses lots of pins but I can program it
reasonably fast with the Xilinx tools. Is this the preferred method?
Or do some of you use 1) proms 2) CPU 3) systemace or other?
Anyone know the 'percentages' of how many users use the different
approaches?

Cheers!
Rich

 

[Gabor]

Rich wrote:

Hello all,

In a seperate thread, there was a brief discussion on what features
are needed in a evaluation kit. So related to that, I'm wondering
what is the preferred method out there for configuring Virtex 5 and
Virtex 6 devices. I"m using commodity parallel flash directly
connected to the FPGA. It uses lots of pins but I can program it
reasonably fast with the Xilinx tools. Is this the preferred method?
Or do some of you use 1) proms 2) CPU 3) systemace or other?
Anyone know the 'percentages' of how many users use the different
approaches?

Cheers!
Rich

For designs where we don't care about configuration time, i.e.
NOT PCI Express, we use commodity SPI flash. Since we almost
always end up IO limited, we never use parallel programming
modes. For faster startup, we use a separate CPLD connected
to possibly multiple SPI flash chips (or fast quad-mode chips)
and a 100 MHz crystal oscillator. The CPLD then uses the slave
serial mode of the V5 at its 100 MHz maximum rate. By the way
this method has uncovered a problem in V5 startup where the
DONE pin doesn't rise fast enough for sampling with the
100 MHz clock, so we ended up enabling the "Internal DONE
Pipe" to prevent a hang-up issue.

Regards,
Gabor

 

[Rich]

On Apr 7, 11:32 am, Gabor <ga...@szakacs.invalid> wrote:

Rich wrote:
Hello all,

In a seperate thread, there was a brief discussion on what features
are needed in a evaluation kit.  So related to that, I'm wondering
what is the preferred method out there for configuring Virtex 5 and
Virtex 6 devices.  I"m using commodity parallel flash directly
connected to the FPGA. It uses lots of pins but I can program it
reasonably fast with the Xilinx tools.   Is this the preferred method?
Or do some of you use 1) proms 2) CPU 3) systemace or other?
Anyone know the 'percentages' of how many users use the different
approaches?

Cheers!
Rich

For designs where we don't care about configuration time, i.e.
NOT PCI Express, we use commodity SPI flash.  Since we almost
always end up IO limited, we never use parallel programming
modes.  For faster startup, we use a separate CPLD connected
to possibly multiple SPI flash chips (or fast quad-mode chips)
and a 100 MHz crystal oscillator.  The CPLD then uses the slave
serial mode of the V5 at its 100 MHz maximum rate.  By the way
this method has uncovered a problem in V5 startup where the
DONE pin doesn't rise fast enough for sampling with the
100 MHz clock, so we ended up enabling the "Internal DONE
Pipe" to prevent a hang-up issue.

Regards,
Gabor

Hello Gabor,
Great! I learned something new. I did leave out SPI, didnt think of
that. I like what you did with multiple SPI and the CPLD. Is there
any difficulty in getting the software to program the SPI via IMPACT/
ISE?

Regards,
Rich

 

[Gabor]

Rich wrote:

On Apr 7, 11:32 am, Gabor <ga...@szakacs.invalid> wrote:
Rich wrote:
Hello all,
In a seperate thread, there was a brief discussion on what features
are needed in a evaluation kit. So related to that, I'm wondering
what is the preferred method out there for configuring Virtex 5 and
Virtex 6 devices. I"m using commodity parallel flash directly
connected to the FPGA. It uses lots of pins but I can program it
reasonably fast with the Xilinx tools. Is this the preferred method?
Or do some of you use 1) proms 2) CPU 3) systemace or other?
Anyone know the 'percentages' of how many users use the different
approaches?
Cheers!
Rich
For designs where we don't care about configuration time, i.e.
NOT PCI Express, we use commodity SPI flash. Since we almost
always end up IO limited, we never use parallel programming
modes. For faster startup, we use a separate CPLD connected
to possibly multiple SPI flash chips (or fast quad-mode chips)
and a 100 MHz crystal oscillator. The CPLD then uses the slave
serial mode of the V5 at its 100 MHz maximum rate. By the way
this method has uncovered a problem in V5 startup where the
DONE pin doesn't rise fast enough for sampling with the
100 MHz clock, so we ended up enabling the "Internal DONE
Pipe" to prevent a hang-up issue.

Regards,
Gabor

Hello Gabor,
Great! I learned something new. I did leave out SPI, didnt think of
that. I like what you did with multiple SPI and the CPLD. Is there
any difficulty in getting the software to program the SPI via IMPACT/
ISE?

Regards,
Rich

In our case we're not even using Xilinx parts for the CPLD's so
we're not programming them with Impact. In fact we use software
on an embedded processor to program the flash parts in system.
But there's no reason you couldn't come up with a way to use
the "direct" SPI program capability of Impact, regardless of
the attachment method. You just need a way to get the CPLD
out of the circuit when the direct programming cable is
plugged in.

Regards,
Gabor