what are some reusable coding practice for rtl design

what are some reusable coding practice for rtl design

why do I see latche sin my synthesized logic

 

[signatrix]

A reusable design mainly help in reducing the design time of larger
implementation using IP
1.register all output of crucial design block this will make the
timing interface easy during system level integration
2.Avoid Glue logic during top level inter module instantiation
3. Avoid instantiation of technology specific gate

4.Following Lexical and naming convention that are self descriptive
and facilitate future product maintenance
5.Use parameters instead of hard- coded values in the design


second

1.the if else clause in the always block to which the latch is
associated does not have a final else clause

for further reference plse mail or refer verilog FAQ

regards

krishnakumar

www.signatrix.in