What am I doing wrong?

E

Ed Diego

Guest
Hi,

I have some VHDL code which tries to set BSY to 1 at the start and then set
it back to 0 at the end. Here is a small sample of the code that does it:

case tx_state is
when IDLE =>
BSY <= '1';

when STATE_LOAD =>
BSY <= '0';

blah
blah
blah



BSY is an external signal defined in the entity part:

entity FSM_entity is
port(BSY : out std_logic;
blah
blah
blah


Im using the XILINX tools to synthersise the code and it generates the
following error:

ERROR:Xst:744 - Failed to build equation for internal node in unit
<fsm_entity>.


If I remove the BSY <= '1' line then it synthersises correctly.

Does anyone know what im doing wrong?

Thanks for any help,
 
In article <beu95u$5mq$1@newsg1.svr.pol.co.uk>,
ed@stevens8436.fslife.co.uk says...
Hi,

I have some VHDL code which tries to set BSY to 1 at the start and then set
it back to 0 at the end. Here is a small sample of the code that does it:

case tx_state is
when IDLE =
BSY <= '1';

when STATE_LOAD =
BSY <= '0';

blah
blah
blah



BSY is an external signal defined in the entity part:

entity FSM_entity is
port(BSY : out std_logic;
blah
blah
blah


Im using the XILINX tools to synthersise the code and it generates the
following error:

ERROR:Xst:744 - Failed to build equation for internal node in unit
fsm_entity>.


If I remove the BSY <= '1' line then it synthersises correctly.

Does anyone know what im doing wrong?
Click to expand...
I don't see anything wrong what what (little) you've posted. Are you
trying to *read* BSY (I.e. BSY on the right side of any equation)
anywhere in your architecture? Since it is an OUT in the entity it
cannot be read.

--
Keith
 
In article <beu9rj$hj3$1@news01.intel.com>,
srinivasan@siliconsystems.no_spam.co.in says...
Hi Ed,
Nothing wrong in the shown part of the code, is it possible that you
leave BSY signal UNASSIGNED in some branches of the case statement? - Just a
blind guess..
Click to expand...
I don't think that's it. A signal being left out of some of the
'when' clauses would simply cause the synthesizer to infer a flip flop
to save the state for the signal in those states.

--
Keith
 
Thanks for the replies,

I put the BSY signal in each of the when statements and I still get the same
error. Also, im not trying to read the BSY signal.

The case statement is inside the following code:

p0: process(TX_CLK)
begin
if(TX_CLK'event and TX_CLK = '1') then
case tx_state is
blah
blah
blah


If I make the two writes to BSY write the same value then the code
synthersizes e.g. both write '1' or both write '0'.

If I take BSY out of the entity part and make it a signal with the following
code:

signal BSY : std_logic;

the code synthersizes. The problem seems to be that BSY is in the entity
part.

Any further ideas? I've looked on google and the XILINX website and could
find no answers.

Thanks again,


"Ed Diego" <ed@stevens8436.fslife.co.uk> wrote in message
news:beu95u$5mq$1@newsg1.svr.pol.co.uk...
Hi,

I have some VHDL code which tries to set BSY to 1 at the start and then
set
it back to 0 at the end. Here is a small sample of the code that does it:

case tx_state is
when IDLE =
BSY <= '1';

when STATE_LOAD =
BSY <= '0';

blah
blah
blah



BSY is an external signal defined in the entity part:

entity FSM_entity is
port(BSY : out std_logic;
blah
blah
blah


Im using the XILINX tools to synthersise the code and it generates the
following error:

ERROR:Xst:744 - Failed to build equation for internal node in unit
fsm_entity>.


If I remove the BSY <= '1' line then it synthersises correctly.

Does anyone know what im doing wrong?

Thanks for any help,
Click to expand...
 
Its finally synthersizing. I had the case statement inside an IF statement.
The IF statement was detecting the rising edge of a clock. I've moved the
IF statement inside each of the WHEN statements and now it seems to
synthersize.

Next time I have a problem I'll post a larger sample of the code so you can
all see what im doing wrong.

Thanks for the advice,

"Ed Diego" <ed@stevens8436.fslife.co.uk> wrote in message
news:beu95u$5mq$1@newsg1.svr.pol.co.uk...
Hi,

I have some VHDL code which tries to set BSY to 1 at the start and then
set
it back to 0 at the end. Here is a small sample of the code that does it:

case tx_state is
when IDLE =
BSY <= '1';

when STATE_LOAD =
BSY <= '0';

blah
blah
blah



BSY is an external signal defined in the entity part:

entity FSM_entity is
port(BSY : out std_logic;
blah
blah
blah


Im using the XILINX tools to synthersise the code and it generates the
following error:

ERROR:Xst:744 - Failed to build equation for internal node in unit
fsm_entity>.


If I remove the BSY <= '1' line then it synthersises correctly.

Does anyone know what im doing wrong?

Thanks for any help,
Click to expand...
 
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