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It's an automatically-generated sensitivity list.Hello,
what is the "always @(*)" expression means in the following code?
always @(*)
begin
if (something_happened) begin
do_something
end
end
On Wed, 25 Jun 2008 05:46:03 -0700 (PDT), japon...@gmail.com wrote:
Hello,
what is the "always @(*)" expression means in the following code?
always @(*)
begin
  if (something_happened) begin
  do_something
  end
end
It's an automatically-generated sensitivity list.
There are some wrinkles and weird details, but for
all practical purposes it looks at the body of its
always block, and builds a sensitivity list from
all variables and nets that the code reads. Â This
is usually what you want for a synthesisable
combinational block.
By the way, it's preferable to use the form without
parentheses:
 always @* begin
  ...
 end
to avoid any possibility of confusion with Verilog
attribute syntax.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Yes, that's probably the most important of the "wrinkles"always @(*)
begin
if (something_happened) begin
do_something
end
end
You should aware of the tasks and functions used in such "always". If
your task/function uses a signal not defined as an input of the task
and no other construction of the "always" uses it either, the
simulation result will be wrong.
You should aware of the tasks and functions used in such "always". IfOn Wed, 25 Jun 2008 05:46:03 -0700 (PDT), japon...@gmail.com wrote:
Hello,
what is the "always @(*)" expression means in the following code?
always @(*)
begin
if (something_happened) begin
do_something
end
end
It's an automatically-generated sensitivity list.
There are some wrinkles and weird details, but for
all practical purposes it looks at the body of its
always block, and builds a sensitivity list from
all variables and nets that the code reads. This
is usually what you want for a synthesisable
combinational block.
By the way, it's preferable to use the form without
parentheses:
always @* begin
...
end
to avoid any possibility of confusion with Verilog
attribute syntax.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Yes. But it's pretty daft to share any such temporaryAnother problem with always @*: shared loop induction variables:
Basically each always @* block needs to have its own induction variables.
Do not share them.