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Is it meaning full to have local params in SV class
SV - System Verilog
SV - System Verilog
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According to the LRM, it's illegal. You probablyIs it meaning full to have local params in SV class
Indeed they have. The current draft of SV-2009Is it meaning full to have local params in SV class
According to the LRM, it's illegal. You probably
want to use a static const instead.
[...]
I have a vague feeling that the rules for this may
have slightly changed in the proposed 2009 standard,