Weird Compile Error

V

~~ VerilogMan ~~

Guest
Hey,
I am gettin an error at this line :
'define counter 1b'0

Error is :

** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Serial_To_Parallel.v(13): near "'d":
syntax error
** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Serial_To_Parallel.v(13): Illegal digit
for specified base in numeric constant



.... NO idea why ??? :(
 
Make sure your define starts with a `grave not a 'single quote' and move the
b for binary to the other side of the tick.

`define counter 1'b0


"~~ VerilogMan ~~" <zoroux7@rogers.com> wrote in message
news:epKdnZM2y_TK0vDcRVn-uA@rogers.com...
Hey,
I am gettin an error at this line :
'define counter 1b'0
[snip]
... NO idea why ??? :(
Click to expand...
 
I suspect there's a line above "input clk;" that isn't properly terminated
with a semicolon. A module declaration port list *does* end with a
semicolon before the external inpu/output/wire/reg definitions.

"~~ VerilogMan ~~" <zoroux7@rogers.com> wrote in message
news:B6SdnVgZ6qOmzvDcRVn-vw@rogers.com...
NICE :) it got fixed but i used to work that way no ?
Now I am getting more errors :|

input clk ;

** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Top_Module_Decoder.v(4): near
"input":
expecting: ';'
Click to expand...
 
John_H wrote:

I suspect there's a line above "input clk;" that isn't
properly terminated with a semicolon.
A module declaration port list *does* end with a
semicolon before the external inpu/output/wire/reg definitions.
Click to expand...
I don't seem to have so much of a problem with semicolons,
though I do still find it a little strange. I remember learning
years ago about the difference between PL/I and Pascal. In PL/I
semicolons are statement terminators, in Pascal they are separators.
The difference appears most around END and ELSE.

Now, why is it that verilog doesn't use them on END?

-- glen
 
The thing is that it's very annoying,
at school my code was working , and now at home I get all these errors ... I
think it's because of the version of ModelSim is not the same :|

--
Sorouche Mirmiran
http://sorouche.no-ip.org
"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
news:ckjor7$16l$1@gnus01.u.washington.edu...
John_H wrote:

I suspect there's a line above "input clk;" that isn't properly
terminated with a semicolon.
A module declaration port list *does* end with a
semicolon before the external inpu/output/wire/reg definitions.

I don't seem to have so much of a problem with semicolons,
though I do still find it a little strange. I remember learning
years ago about the difference between PL/I and Pascal. In PL/I
semicolons are statement terminators, in Pascal they are separators.
The difference appears most around END and ELSE.

Now, why is it that verilog doesn't use them on END?

-- glen
Click to expand...
 
YAE (yet another error !)

always@(count or clk_div)
if(count==6)
begin
count = 0;

** Error: D:/DATA/School/478/Verilog/clock_divider.v(21): (vlog-2110)
Illegal reference to net "count".

--
Sorouche Mirmiran
http://sorouche.no-ip.org
"John_H" <johnhandwork@mail.com> wrote in message
news:Hmebd.13$vk2.1625@news-west.eli.net...
You have so much stuff that should never have worked anywhere.
Inputs have the range before the identifier. 2-D inputs are not supported
in Verilog. So...

input [1:0] parallel_data;

is the "encoded_w_errors_out = encoded_w_errors;" supposed to be a
continuous assignment or is it in an always block, using the unusual
blocking operator?

This almost looks like something a prof would give to find out how little
someone actually knows about Verilog. Do you have a coworker that could
look over your shoulder as opposed to spending time here fixing your code?


"~~ VerilogMan ~~" <zoroux7@rogers.com> wrote in message
news:cpKdndPNKr5m9PDcRVn-uQ@rogers.com...
Correct, i had forgotten a ";" at the end of my module declaration ! :)
I get a lot of errors with this type of statement:

input parallel_data[1:0];
** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Top_Module_Decoder.v(7): near "[":
expecting: ';'


and another error :
encoded_w_errors_out = encoded_w_errors;

** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Top_Module_Decoder.v(33): near "=":
expecting: IDENT
Click to expand...
 
Make your partner fix his non-working code.

ANYTHING assigned in an always block either with a plocking operator or a
non-blocking operator cannot be a type wire. Typically the reg is used but
I believe integers would work as well.

This is super-simple Verilog. You should know this if you're "Verilog Man."
If your partner doesn't have it right, have him fix the code or get rid of
him - you're better off doing it right the first time than correcting his
mistakes.

I like to help people out but I'll bow out of further comments on your
errors. Good luck, man.


"~~ VerilogMan ~~" <zoroux7@rogers.com> wrote in message
news:yqednb7lu6KbEvDcRVn-tA@rogers.com...
YAE (yet another error !)

always@(count or clk_div)
if(count==6)
begin
count = 0;

** Error: D:/DATA/School/478/Verilog/clock_divider.v(21): (vlog-2110)
Illegal reference to net "count".

--
Sorouche Mirmiran
http://sorouche.no-ip.org
"John_H" <johnhandwork@mail.com> wrote in message
news:Hmebd.13$vk2.1625@news-west.eli.net...
You have so much stuff that should never have worked anywhere.
Inputs have the range before the identifier. 2-D inputs are not
supported
in Verilog. So...

input [1:0] parallel_data;

is the "encoded_w_errors_out = encoded_w_errors;" supposed to be a
continuous assignment or is it in an always block, using the unusual
blocking operator?

This almost looks like something a prof would give to find out how
little
someone actually knows about Verilog. Do you have a coworker that could
look over your shoulder as opposed to spending time here fixing your
code?


"~~ VerilogMan ~~" <zoroux7@rogers.com> wrote in message
news:cpKdndPNKr5m9PDcRVn-uQ@rogers.com...
Correct, i had forgotten a ";" at the end of my module declaration !
:)
I get a lot of errors with this type of statement:

input parallel_data[1:0];
** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Top_Module_Decoder.v(7): near "[":
expecting: ';'


and another error :
encoded_w_errors_out = encoded_w_errors;

** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Top_Module_Decoder.v(33): near
"=":
expecting: IDENT
Click to expand...
 
NICE :) it got fixed but i used to work that way no ?
Now I am getting more errors :|

input clk ;

** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Top_Module_Decoder.v(4): near "input":
expecting: ';'


--
Sorouche Mirmiran
http://sorouche.no-ip.org
"John_H" <johnhandwork@mail.com> wrote in message
news:Wicbd.9$vk2.1200@news-west.eli.net...
Make sure your define starts with a `grave not a 'single quote' and move
the
b for binary to the other side of the tick.

`define counter 1'b0


"~~ VerilogMan ~~" <zoroux7@rogers.com> wrote in message
news:epKdnZM2y_TK0vDcRVn-uA@rogers.com...
Hey,
I am gettin an error at this line :
'define counter 1b'0
[snip]
... NO idea why ??? :(
Click to expand...
 
Correct, i had forgotten a ";" at the end of my module declaration ! :)
I get a lot of errors with this type of statement:

input parallel_data[1:0];
** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Top_Module_Decoder.v(7): near "[":
expecting: ';'


and another error :
encoded_w_errors_out = encoded_w_errors;

** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Top_Module_Decoder.v(33): near "=":
expecting: IDENT


"John_H" <johnhandwork@mail.com> wrote in message
news:Dbdbd.12$vk2.1634@news-west.eli.net...
I suspect there's a line above "input clk;" that isn't properly terminated
with a semicolon. A module declaration port list *does* end with a
semicolon before the external inpu/output/wire/reg definitions.

"~~ VerilogMan ~~" <zoroux7@rogers.com> wrote in message
news:B6SdnVgZ6qOmzvDcRVn-vw@rogers.com...
NICE :) it got fixed but i used to work that way no ?
Now I am getting more errors :|

input clk ;

** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Top_Module_Decoder.v(4): near
"input":
expecting: ';'
Click to expand...
 
You have so much stuff that should never have worked anywhere.
Inputs have the range before the identifier. 2-D inputs are not supported
in Verilog. So...

input [1:0] parallel_data;

is the "encoded_w_errors_out = encoded_w_errors;" supposed to be a
continuous assignment or is it in an always block, using the unusual
blocking operator?

This almost looks like something a prof would give to find out how little
someone actually knows about Verilog. Do you have a coworker that could
look over your shoulder as opposed to spending time here fixing your code?


"~~ VerilogMan ~~" <zoroux7@rogers.com> wrote in message
news:cpKdndPNKr5m9PDcRVn-uQ@rogers.com...
Correct, i had forgotten a ";" at the end of my module declaration ! :)
I get a lot of errors with this type of statement:

input parallel_data[1:0];
** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Top_Module_Decoder.v(7): near "[":
expecting: ';'


and another error :
encoded_w_errors_out = encoded_w_errors;

** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Top_Module_Decoder.v(33): near "=":
expecting: IDENT
Click to expand...
[snip]
 
No, to be honest, this is not my code man , we trying to build a convolution
encoder
Each of us has to do part of the code... I did mine ,....
And I am supposed to do the testbench too ...
But all the stuff my partner sent are half not working ! He has his own way
of coding... and it's a pain to look for the errors
I have been over his codes for the whole day ... and I have to do get my tb
done for trw :|


--
Sorouche Mirmiran
http://sorouche.no-ip.org

"John_H" <johnhandwork@mail.com> wrote in message
news:Hmebd.13$vk2.1625@news-west.eli.net...
You have so much stuff that should never have worked anywhere.
Inputs have the range before the identifier. 2-D inputs are not supported
in Verilog. So...

input [1:0] parallel_data;

is the "encoded_w_errors_out = encoded_w_errors;" supposed to be a
continuous assignment or is it in an always block, using the unusual
blocking operator?

This almost looks like something a prof would give to find out how little
someone actually knows about Verilog. Do you have a coworker that could
look over your shoulder as opposed to spending time here fixing your code?


"~~ VerilogMan ~~" <zoroux7@rogers.com> wrote in message
news:cpKdndPNKr5m9PDcRVn-uQ@rogers.com...
Correct, i had forgotten a ";" at the end of my module declaration ! :)
I get a lot of errors with this type of statement:

input parallel_data[1:0];
** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Top_Module_Decoder.v(7): near "[":
expecting: ';'


and another error :
encoded_w_errors_out = encoded_w_errors;

** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Top_Module_Decoder.v(33): near "=":
expecting: IDENT

[snip]
Click to expand...
 
My lab partner is my friend ... can't get rid of them...
I found already *a lot* of errors, but after a while especially when it is
not your code, you don't see everything ...
thanks anyways

PS: I am verilog man , because I will be a verilog master
:)

--
Sorouche Mirmiran
http://sorouche.no-ip.org
"John_H" <johnhandwork@mail.com> wrote in message
news:xpgbd.18$vk2.1674@news-west.eli.net...
Make your partner fix his non-working code.

ANYTHING assigned in an always block either with a plocking operator or a
non-blocking operator cannot be a type wire. Typically the reg is used
but
I believe integers would work as well.

This is super-simple Verilog. You should know this if you're "Verilog
Man."
If your partner doesn't have it right, have him fix the code or get rid of
him - you're better off doing it right the first time than correcting his
mistakes.

I like to help people out but I'll bow out of further comments on your
errors. Good luck, man.


"~~ VerilogMan ~~" <zoroux7@rogers.com> wrote in message
news:yqednb7lu6KbEvDcRVn-tA@rogers.com...
YAE (yet another error !)

always@(count or clk_div)
if(count==6)
begin
count = 0;

** Error: D:/DATA/School/478/Verilog/clock_divider.v(21): (vlog-2110)
Illegal reference to net "count".

--
Sorouche Mirmiran
http://sorouche.no-ip.org
"John_H" <johnhandwork@mail.com> wrote in message
news:Hmebd.13$vk2.1625@news-west.eli.net...
You have so much stuff that should never have worked anywhere.
Inputs have the range before the identifier. 2-D inputs are not
supported
in Verilog. So...

input [1:0] parallel_data;

is the "encoded_w_errors_out = encoded_w_errors;" supposed to be a
continuous assignment or is it in an always block, using the unusual
blocking operator?

This almost looks like something a prof would give to find out how
little
someone actually knows about Verilog. Do you have a coworker that
could
look over your shoulder as opposed to spending time here fixing your
code?


"~~ VerilogMan ~~" <zoroux7@rogers.com> wrote in message
news:cpKdndPNKr5m9PDcRVn-uQ@rogers.com...
Correct, i had forgotten a ";" at the end of my module declaration !
:)
I get a lot of errors with this type of statement:

input parallel_data[1:0];
** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Top_Module_Decoder.v(7): near
"[":
expecting: ';'


and another error :
encoded_w_errors_out = encoded_w_errors;

** Error: C:/Documents and
Settings/Zoroastreus/Desktop/Verilog/Top_Module_Decoder.v(33): near
"=":
expecting: IDENT
Click to expand...
 
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