Weird ADC block diagram: LTC2351...

[Phil Hobbs]

So I\'m building this multiple sample/hold thing using those sub-100 ps
pHEMT samplers I was talking about in another thread, plus a
simultaneous-sampling ADC, the six-channel LTC2351-14.

It\'s quite a nice part--100 MHz analog bandwidth, 200 ps skew, and
decent linearity, but its datasheet has a strange block diagram.

<https://www.analog.com/media/en/technical-documentation/data-sheets/235114fb.pdf>

Right there on P. 1, it shows six T/Hs, a mux, an ADC with internal
reference, and *six 14-bit registers*.

\"Aha,\" says I, \"it\'s one of those swoopy internally-clocked gizmos,so
you just have to wait for !BUSY and read out the registers at your
leisure. Just the thing for the job!\"

Turns out it ain\'t so--it requires 96 SPI clocks to do the conversion
and read out the data.

So what d\'ya s\'pose the registers are for, if they even exist? Was the
marketing guy on crack?

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[John Larkin]

On Wed, 16 Sep 2020 15:06:43 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

So I\'m building this multiple sample/hold thing using those sub-100 ps
pHEMT samplers I was talking about in another thread, plus a
simultaneous-sampling ADC, the six-channel LTC2351-14.

It\'s quite a nice part--100 MHz analog bandwidth, 200 ps skew, and
decent linearity, but its datasheet has a strange block diagram.

https://www.analog.com/media/en/technical-documentation/data-sheets/235114fb.pdf

Right there on P. 1, it shows six T/Hs, a mux, an ADC with internal
reference, and *six 14-bit registers*.

\"Aha,\" says I, \"it\'s one of those swoopy internally-clocked gizmos,so
you just have to wait for !BUSY and read out the registers at your
leisure. Just the thing for the job!\"

Turns out it ain\'t so--it requires 96 SPI clocks to do the conversion
and read out the data.

So what d\'ya s\'pose the registers are for, if they even exist? Was the
marketing guy on crack?

Cheers

Phil Hobbs

Some ADCs actually do the SAR conversion as the SPI data is being
clocked out. So there is no actual data register.

But in this one, the s/h blocks are presumably drifting, so it makes
sense to convert as fast as possible, and to always have the same
timing, to have consistent drift-driven offsets. Maybe they really do
the conversions when CONV rises, and stash the data in registers ASAP.

Full disclosure, I haven\'t read every word of the data sheet.

Don\'t the least promising interns write the data sheets?

 

[Lasse Langwadt Christensen]

onsdag den 16. september 2020 kl. 21.06.54 UTC+2 skrev Phil Hobbs:

So I\'m building this multiple sample/hold thing using those sub-100 ps
pHEMT samplers I was talking about in another thread, plus a
simultaneous-sampling ADC, the six-channel LTC2351-14.

It\'s quite a nice part--100 MHz analog bandwidth, 200 ps skew, and
decent linearity, but its datasheet has a strange block diagram.

https://www.analog.com/media/en/technical-documentation/data-sheets/235114fb.pdf

Right there on P. 1, it shows six T/Hs, a mux, an ADC with internal
reference, and *six 14-bit registers*.

\"Aha,\" says I, \"it\'s one of those swoopy internally-clocked gizmos,so
you just have to wait for !BUSY and read out the registers at your
leisure. Just the thing for the job!\"

Turns out it ain\'t so--it requires 96 SPI clocks to do the conversion
and read out the data.

So what d\'ya s\'pose the registers are for, if they even exist? Was the
marketing guy on crack?

it is confusing, as far as I can tell you can set it up for less that
6 channels and only clock 16x times the number of channels to convert those channels but you can always clock 96 times the data in the channels not setup to convert will just be old data

 

[Joe Gwinn]

On Wed, 16 Sep 2020 15:06:43 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

So I\'m building this multiple sample/hold thing using those sub-100 ps
pHEMT samplers I was talking about in another thread, plus a
simultaneous-sampling ADC, the six-channel LTC2351-14.

It\'s quite a nice part--100 MHz analog bandwidth, 200 ps skew, and
decent linearity, but its datasheet has a strange block diagram.

https://www.analog.com/media/en/technical-documentation/data-sheets/235114fb.pdf

Right there on P. 1, it shows six T/Hs, a mux, an ADC with internal
reference, and *six 14-bit registers*.

\"Aha,\" says I, \"it\'s one of those swoopy internally-clocked gizmos,so
you just have to wait for !BUSY and read out the registers at your
leisure. Just the thing for the job!\"

Turns out it ain\'t so--it requires 96 SPI clocks to do the conversion
and read out the data.

So what d\'ya s\'pose the registers are for, if they even exist? Was the
marketing guy on crack?

What I think is happening is that all six s/h units take a sample
simultaneously, and during hold the six anamog signals are routed to
the shared ADC, with results sored in the corresponding 14-bit
registers, which are then read out serially. The next conversion
cannot happen until this read-out is complete. If one chooses to ues
fewer than 6 channels, this process is proportionally faster.

Joe Gwinn

 

[Ricketty C]

On Wednesday, September 16, 2020 at 7:08:33 PM UTC-4, Joe Gwinn wrote:

On Wed, 16 Sep 2020 15:06:43 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

So I\'m building this multiple sample/hold thing using those sub-100 ps
pHEMT samplers I was talking about in another thread, plus a
simultaneous-sampling ADC, the six-channel LTC2351-14.

It\'s quite a nice part--100 MHz analog bandwidth, 200 ps skew, and
decent linearity, but its datasheet has a strange block diagram.

https://www.analog.com/media/en/technical-documentation/data-sheets/235114fb.pdf

Right there on P. 1, it shows six T/Hs, a mux, an ADC with internal
reference, and *six 14-bit registers*.

\"Aha,\" says I, \"it\'s one of those swoopy internally-clocked gizmos,so
you just have to wait for !BUSY and read out the registers at your
leisure. Just the thing for the job!\"

Turns out it ain\'t so--it requires 96 SPI clocks to do the conversion
and read out the data.

So what d\'ya s\'pose the registers are for, if they even exist? Was the
marketing guy on crack?

What I think is happening is that all six s/h units take a sample
simultaneously, and during hold the six anamog signals are routed to
the shared ADC, with results sored in the corresponding 14-bit
registers, which are then read out serially. The next conversion
cannot happen until this read-out is complete. If one chooses to ues
fewer than 6 channels, this process is proportionally faster.

Joe Gwinn

I believe this device overlaps the conversions and and the readouts. But you can not shorten the sample time and increase the conversion rate by converting fewer channels. There is a minimum spec of 4 us. The entire set of selected channels are converted and saved as you read out the previous set of data. Then you read that set of converted data. So there is a latency of 4 us to get your data. Like Larkin said, it is probably converting using the interface clock. They specifically say that if the number of channels selected is changed, the old data that hasn\'t been read out will remain so it can be retrieved when the selected channel count is changed back.

Funny part. If they weren\'t a small fortune I\'d consider using them.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

[Tim Williams]

Seems to be the externally-clocked kind, but you can keep going for longer
than needed (i.e., 16*N clocks for N channels, in order starting from 0),
perhaps to keep the interface constant (no need for, say, address bits to
select what channel to read from). Which will have savings both in logic,
and the user\'s driver.

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/

\"Phil Hobbs\" <pcdhSpamMeSenseless@electrooptical.net> wrote in message
news:d1799f20-2923-b777-c5ef-161d1697400f@electrooptical.net...

So I\'m building this multiple sample/hold thing using those sub-100 ps
pHEMT samplers I was talking about in another thread, plus a
simultaneous-sampling ADC, the six-channel LTC2351-14.

It\'s quite a nice part--100 MHz analog bandwidth, 200 ps skew, and decent
linearity, but its datasheet has a strange block diagram.

https://www.analog.com/media/en/technical-documentation/data-sheets/235114fb.pdf

Right there on P. 1, it shows six T/Hs, a mux, an ADC with internal
reference, and *six 14-bit registers*.

\"Aha,\" says I, \"it\'s one of those swoopy internally-clocked gizmos,so you
just have to wait for !BUSY and read out the registers at your leisure.
Just the thing for the job!\"

Turns out it ain\'t so--it requires 96 SPI clocks to do the conversion and
read out the data.

So what d\'ya s\'pose the registers are for, if they even exist? Was the
marketing guy on crack?

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Phil Hobbs]

On 2020-09-17 00:56, Tim Williams wrote:

Seems to be the externally-clocked kind, but you can keep going for
longer than needed (i.e., 16*N clocks for N channels, in order starting
from 0), perhaps to keep the interface constant (no need for, say,
address bits to select what channel to read from).  Which will have
savings both in logic, and the user\'s driver.

Tim

I\'m coming to the view that it\'s a normal SPI-clocked one, and that the
drawing is just plain wrong. If it were internally clocked, there\'d be
no reason I can see for the requirement that the SPI clock start within
10 us of the CONV pulse.

We\'re going to try it out this afternoon and see if we can measure its
droop vs. delay time.

Thanks

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[John Larkin]

On Thu, 17 Sep 2020 12:32:58 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2020-09-17 00:56, Tim Williams wrote:
Seems to be the externally-clocked kind, but you can keep going for
longer than needed (i.e., 16*N clocks for N channels, in order starting
from 0), perhaps to keep the interface constant (no need for, say,
address bits to select what channel to read from).  Which will have
savings both in logic, and the user\'s driver.

Tim


I\'m coming to the view that it\'s a normal SPI-clocked one, and that the
drawing is just plain wrong. If it were internally clocked, there\'d be
no reason I can see for the requirement that the SPI clock start within
10 us of the CONV pulse.

We\'re going to try it out this afternoon and see if we can measure its
droop vs. delay time.

Thanks

Phil Hobbs

You could hang a fet probe on top of the chip, maybe on a foil
sticker, and see if it clocks itself at CONV time. I worked once with
some people who were trying to identify counterfeit chips this way.
Lots of chips leak visible signal.

I suggested that they measure wideband VCC current too.

I guess s/h droop is the bottom line. You could wait seconds, or
hours.

There are some interesting DDG architectures that need fast, low droop
s/h\'s. None work really well.

 

[Ricketty C]

On Thursday, September 17, 2020 at 12:33:09 PM UTC-4, Phil Hobbs wrote:

On 2020-09-17 00:56, Tim Williams wrote:
Seems to be the externally-clocked kind, but you can keep going for
longer than needed (i.e., 16*N clocks for N channels, in order starting
from 0), perhaps to keep the interface constant (no need for, say,
address bits to select what channel to read from).  Which will have
savings both in logic, and the user\'s driver.

Tim


I\'m coming to the view that it\'s a normal SPI-clocked one, and that the
drawing is just plain wrong. If it were internally clocked, there\'d be
no reason I can see for the requirement that the SPI clock start within
10 us of the CONV pulse.

We\'re going to try it out this afternoon and see if we can measure its
droop vs. delay time.

I don\'t know why you say the \"drawing\" is wrong. They clearly show a block \"timing\" that receives the SPI clock and drives the ADC. Everything I\'ve seen in the data sheet shows the device IS clocking the ADC from the SPI clock. The main issue is that the data you are clocking out is not from this conversion, but from the previous conversion. That\'s why it has N registers rather than just one.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

 

[Phil Hobbs]

On 2020-09-16 15:38, John Larkin wrote:

On Wed, 16 Sep 2020 15:06:43 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

So I\'m building this multiple sample/hold thing using those sub-100 ps
pHEMT samplers I was talking about in another thread, plus a
simultaneous-sampling ADC, the six-channel LTC2351-14.

It\'s quite a nice part--100 MHz analog bandwidth, 200 ps skew, and
decent linearity, but its datasheet has a strange block diagram.

https://www.analog.com/media/en/technical-documentation/data-sheets/235114fb.pdf

Right there on P. 1, it shows six T/Hs, a mux, an ADC with internal
reference, and *six 14-bit registers*.

\"Aha,\" says I, \"it\'s one of those swoopy internally-clocked gizmos,so
you just have to wait for !BUSY and read out the registers at your
leisure. Just the thing for the job!\"

Turns out it ain\'t so--it requires 96 SPI clocks to do the conversion
and read out the data.

So what d\'ya s\'pose the registers are for, if they even exist? Was the
marketing guy on crack?

Cheers

Phil Hobbs

Some ADCs actually do the SAR conversion as the SPI data is being
clocked out. So there is no actual data register.

But in this one, the s/h blocks are presumably drifting, so it makes
sense to convert as fast as possible, and to always have the same
timing, to have consistent drift-driven offsets. Maybe they really do
the conversions when CONV rises, and stash the data in registers ASAP.

Full disclosure, I haven\'t read every word of the data sheet.

There\'s an analogue-ish 10 us maximum time delay between CONV and the
first SPI clock, with a 10-us maximum clock period. So one is allowed
at most a millisecond or so to finish the whole conversion/readout cycle.

We\'re going to try it out and see.

Don\'t the least promising interns write the data sheets?

Could be the most promising ones. (*)

Cheers

Phil Hobbs

\"Calypso and reggae are the same. A reggae band can afford better drugs
is all.\"



--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Phil Hobbs]

On 2020-09-17 13:33, John Larkin wrote:

On Thu, 17 Sep 2020 12:32:58 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2020-09-17 00:56, Tim Williams wrote:
Seems to be the externally-clocked kind, but you can keep going for
longer than needed (i.e., 16*N clocks for N channels, in order starting
from 0), perhaps to keep the interface constant (no need for, say,
address bits to select what channel to read from).  Which will have
savings both in logic, and the user\'s driver.

Tim


I\'m coming to the view that it\'s a normal SPI-clocked one, and that the
drawing is just plain wrong. If it were internally clocked, there\'d be
no reason I can see for the requirement that the SPI clock start within
10 us of the CONV pulse.

We\'re going to try it out this afternoon and see if we can measure its
droop vs. delay time.

Thanks

Phil Hobbs

You could hang a fet probe on top of the chip, maybe on a foil
sticker, and see if it clocks itself at CONV time. I worked once with
some people who were trying to identify counterfeit chips this way.
Lots of chips leak visible signal.

I suggested that they measure wideband VCC current too.

Interesting idea--we\'ll try that while we\'re waiting.

I guess s/h droop is the bottom line. You could wait seconds, or
hours.

There are some interesting DDG architectures that need fast, low droop
s/h\'s. None work really well.

Well, if you can guarantee a sufficient delay between acquisition and
readout, you can do a pretty good job with a fast droopy one followed by
a slower non-droopy one. (You knew that already.)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[John Larkin]

On Thu, 17 Sep 2020 14:08:21 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2020-09-17 13:33, John Larkin wrote:
On Thu, 17 Sep 2020 12:32:58 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2020-09-17 00:56, Tim Williams wrote:
Seems to be the externally-clocked kind, but you can keep going for
longer than needed (i.e., 16*N clocks for N channels, in order starting
from 0), perhaps to keep the interface constant (no need for, say,
address bits to select what channel to read from).  Which will have
savings both in logic, and the user\'s driver.

Tim


I\'m coming to the view that it\'s a normal SPI-clocked one, and that the
drawing is just plain wrong. If it were internally clocked, there\'d be
no reason I can see for the requirement that the SPI clock start within
10 us of the CONV pulse.

We\'re going to try it out this afternoon and see if we can measure its
droop vs. delay time.

Thanks

Phil Hobbs

You could hang a fet probe on top of the chip, maybe on a foil
sticker, and see if it clocks itself at CONV time. I worked once with
some people who were trying to identify counterfeit chips this way.
Lots of chips leak visible signal.

I suggested that they measure wideband VCC current too.

Interesting idea--we\'ll try that while we\'re waiting.


I guess s/h droop is the bottom line. You could wait seconds, or
hours.

There are some interesting DDG architectures that need fast, low droop
s/h\'s. None work really well.

Well, if you can guarantee a sufficient delay between acquisition and
readout, you can do a pretty good job with a fast droopy one followed by
a slower non-droopy one. (You knew that already.)

Cheers

Phil Hobbs

Been there, done that, still having PTSD.

 

[Phil Hobbs]

On 2020-09-17 14:04, Ricketty C wrote:

On Thursday, September 17, 2020 at 12:33:09 PM UTC-4, Phil Hobbs
wrote:
On 2020-09-17 00:56, Tim Williams wrote:
Seems to be the externally-clocked kind, but you can keep going
for longer than needed (i.e., 16*N clocks for N channels, in
order starting from 0), perhaps to keep the interface constant
(no need for, say, address bits to select what channel to read
from). Which will have savings both in logic, and the user\'s
driver.

Tim


I\'m coming to the view that it\'s a normal SPI-clocked one, and that
the drawing is just plain wrong. If it were internally clocked,
there\'d be no reason I can see for the requirement that the SPI
clock start within 10 us of the CONV pulse.

We\'re going to try it out this afternoon and see if we can measure
its droop vs. delay time.

I don\'t know why you say the \"drawing\" is wrong. They clearly show a
block \"timing\" that receives the SPI clock and drives the ADC.
Everything I\'ve seen in the data sheet shows the device IS clocking
the ADC from the SPI clock. The main issue is that the data you are
clocking out is not from this conversion, but from the previous
conversion. That\'s why it has N registers rather than just one.

Thanks for playing.

Cheers

Phil Hobbs

 

[Chris Jones]

On 18/09/2020 02:32, Phil Hobbs wrote:

On 2020-09-17 00:56, Tim Williams wrote:
Seems to be the externally-clocked kind, but you can keep going for
longer than needed (i.e., 16*N clocks for N channels, in order
starting from 0), perhaps to keep the interface constant (no need for,
say, address bits to select what channel to read from).  Which will
have savings both in logic, and the user\'s driver.

Tim


I\'m coming to the view that it\'s a normal SPI-clocked one, and that the
drawing is just plain wrong.  If it were internally clocked, there\'d be
no reason I can see for the requirement that the SPI clock start within
10 us of the CONV pulse.

We\'re going to try it out this afternoon and see if we can measure its
droop vs. delay time.

If the droop is measurable, then it might be easier to measure near the
highest rated operating temperature, as of course the leakage should be
much lower at room temperature.

 

[server]

On Thu, 17 Sep 2020 19:31:34 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2020-09-17 14:04, Ricketty C wrote:
On Thursday, September 17, 2020 at 12:33:09 PM UTC-4, Phil Hobbs
wrote:
On 2020-09-17 00:56, Tim Williams wrote:
Seems to be the externally-clocked kind, but you can keep going
for longer than needed (i.e., 16*N clocks for N channels, in
order starting from 0), perhaps to keep the interface constant
(no need for, say, address bits to select what channel to read
from). Which will have savings both in logic, and the user\'s
driver.

Tim


I\'m coming to the view that it\'s a normal SPI-clocked one, and that
the drawing is just plain wrong. If it were internally clocked,
there\'d be no reason I can see for the requirement that the SPI
clock start within 10 us of the CONV pulse.

We\'re going to try it out this afternoon and see if we can measure
its droop vs. delay time.

I don\'t know why you say the \"drawing\" is wrong. They clearly show a
block \"timing\" that receives the SPI clock and drives the ADC.
Everything I\'ve seen in the data sheet shows the device IS clocking
the ADC from the SPI clock. The main issue is that the data you are
clocking out is not from this conversion, but from the previous
conversion. That\'s why it has N registers rather than just one.


Thanks for playing.

Cheers

Phil Hobbs

Most of ricky\'s posts are variations on \"I don\'t understand why you
are so stupid.\"

He doesn\'t ever play.



--

John Larkin Highland Technology, Inc

Science teaches us to doubt.

Claude Bernard

 

[Piotr Wyderski]

Phil Hobbs wrote:

> So what d\'ya s\'pose the registers are for, if they even exist?

They seem to exist, as it is stated at the front page figure, then
repeated at page 9., then mentioned in the text at page 17, then
confirmed by the timing diagram at page 10.

They seem to use the CONV-centric approach, which they usually do
anyway, not the SCK alone.

\"The rising edge of CONV starts a conversion, but subsequent rising
edges at CONV are ignored by the LTC2351-14 until the following 96 SCK
rising edges have occurred.\"

Combining that with the timing diagram shows that they expect 96 SCK
cycles to be provided after the CONV trigger is activated, and they will
not start talking to you sooner than that. So that implies that the
96-bit latch is real, as it is necessary to implement this interface.

Another question is why they would want such a twisted interface to
begin with. I have no idea, but my SWAG would follow the Sleep and NAP
shutdown modes, which are also controlled by CONV/SCK. Micropower
delay-tolerant micropower conversions? Ask them.

Best regards, Piotr