Weird 2D-array issue

[Michael Meeuwisse]

Hi,

I'm still not that familiar with verilog and am getting some weird
errors. Hopefully somebody can make some sense out of them because
google can't.

I have:
reg [1: 0] cmd [1: 0];
And during reset want to do:
cmd <= 0;

When checking syntax (Xilinx Webpack 10.1.01) This gives "Illegal left
hand side of nonblocking assignment" which is really annoying. I figured
I could do something like this:
{cmd[0], cmd[1], cmd[2], cmd[3]} <= 0;

But this gives the warning (twice, for 2 & 3) "Index 1 in word-select of
vector reg array 'cmd' is out of range". Ehm, no? It isn't, is it?

Thanks in advance,


Michael

 

[John_H]

Michael Meeuwisse wrote:

Hi,

I'm still not that familiar with verilog and am getting some weird
errors. Hopefully somebody can make some sense out of them because
google can't.

I have:
reg [1: 0] cmd [1: 0];
And during reset want to do:
cmd <= 0;

When checking syntax (Xilinx Webpack 10.1.01) This gives "Illegal left
hand side of nonblocking assignment" which is really annoying. I figured
I could do something like this:
{cmd[0], cmd[1], cmd[2], cmd[3]} <= 0;

But this gives the warning (twice, for 2 & 3) "Index 1 in word-select of
vector reg array 'cmd' is out of range". Ehm, no? It isn't, is it?

Thanks in advance,


Michael

Do you expect 4 bits in your 2x2 array to require 4 1-D indicies? You
have two 2-bit vectors:

{cmd[0], cmd[1]} <= 4'h0;

 

[Michael Meeuwisse]

John_H wrote:

Do you expect 4 bits in your 2x2 array to require 4 1-D indicies? You
have two 2-bit vectors:

{cmd[0], cmd[1]} <= 4'h0;

No, I expect four 2-bit vectors. I've got [1: 0] = 2 bits, and [1: 0] =
2 bits = 4 addresses, right?


Michael

 

[Michael Meeuwisse]

gabor wrote:

On Jul 1, 9:37 am, Michael Meeuwisse <mickeymeeuw@no_spam_gmail
wrote:
No, I expect four 2-bit vectors. I've got [1: 0] = 2 bits, and [1: 0] =
2 bits = 4 addresses, right?

Michael

Wrong. [1:0] is defining two bits and the second [1:0] defines two
vectors. If you want 2 bits of address you need 4 vectors like
reg [1:0] cmd [0:3]; // Memory is usually defined from 0 up rather
than 3 down

Ah yeez. That's about as counter-intuitive as it can get. Oh well,
thanks anyway. Seems to be working.


Michael

 

[gabor]

On Jul 1, 9:37 am, Michael Meeuwisse <mickeymeeuw@no_spam_gmail>
wrote:

John_H wrote:
Do you expect 4 bits in your 2x2 array to require 4 1-D indicies? You
have two 2-bit vectors:

{cmd[0], cmd[1]} <= 4'h0;

No, I expect four 2-bit vectors. I've got [1: 0] = 2 bits, and [1: 0] =
2 bits = 4 addresses, right?

Michael

Wrong. [1:0] is defining two bits and the second [1:0] defines two
vectors. If you want 2 bits of address you need 4 vectors like
reg [1:0] cmd [0:3]; // Memory is usually defined from 0 up rather
than 3 down

 

[Mike Treseler]

Michael Meeuwisse wrote:

Ah yeez. That's about as counter-intuitive as it can get. Oh well,
thanks anyway. Seems to be working.

Michael:

Consider what the phrase "thanks anyway" connotes to the reader.

-- Mike Treseler

 

[Michael Meeuwisse]

John_H wrote:

But it's not a counter, it's a memory.

Consider: if you wanted a memory structure of 23 bytes, how would you
want to specify it in Verilog? Would you prefer the language dictate
that all memory elements must be 2^n in size?

True. It does make sense, I just hadn't encountered it yet in any
tutorial and assumed it worked the same way as when defining an array.

Mike Treseler wrote:

Consider what the phrase "thanks anyway" connotes to the reader.

I was trying to:
0) make a complaint about the ambiguity of the subject
1) thank gabor anyway for helping me understand it

Yes, I know you can interpret it differently:
1) I thanked gabor anyway for trying to help me out, but ultimately
failing to do so.
Which was not the case and I didn't intend to. Can we move this to
human.lang.english?

Thanks.


Michael

 

[John_H]

Michael Meeuwisse wrote:

Ah yeez. That's about as counter-intuitive as it can get. Oh well,
thanks anyway. Seems to be working.


Michael

But it's not a counter, it's a memory.

Consider: if you wanted a memory structure of 23 bytes, how would you
want to specify it in Verilog? Would you prefer the language dictate
that all memory elements must be 2^n in size?

 

[John_H]

Michael Meeuwisse wrote:

I was trying to:
0) make a complaint about the ambiguity of the subject
1) thank gabor anyway for helping me understand it

Consider that there isn't ambiguity in the subject. You chose to make
it ambiguous.

Consider what I asked:

reg [7:0] mem [0:22];

This implies that you have 8 data BITS per memory element. The fact
that you can represent 256 levels with 8 bits is irrelevant. There
are 8 storage elements corresponding to one byte, not 256. In the
same fashion, you'd want a 2-D array of 8 by 23 storage elements for a
total of 184. Now how the heck would any engineer thinking beyond the
fact that he has a 2-bit address think they could get away with this?
To get 8 bits, you don't use a 3-bit mux select after all, you specify
the elements.

The ambiguity is all yours.

Whatever,