weak pull up and pull down

Hello
I have a Verilog model that uses

rtran(P_P, PADP_i);
rtran(P_M, PADM_i);

If I model this in VHDL, P_P and P_M are pulled up and down and I
cannot use signal assignments in VITAL as I am in a process which
complains if I do so. How do I model these in VITAL in VHDL?

Thanks
krithiga

 

Hello
Can someone please respond to my posting?

Thanks
krithiga

krithiga81@yahoo.com wrote:

Hello
I have a Verilog model that uses

rtran(P_P, PADP_i);
rtran(P_M, PADM_i);

If I model this in VHDL, P_P and P_M are pulled up and down and I
cannot use signal assignments in VITAL as I am in a process which
complains if I do so. How do I model these in VITAL in VHDL?

Thanks
krithiga

 

[Mike Treseler]

krithiga81@yahoo.com wrote:

Hello
Can someone please respond to my posting?

Perhaps there are no newsgroup readers
who know verilog and vhdl and VITAL models.

-- Mike Treseler