ways to find frequency of operation in early phase of the de

[Vips]

Hello All ,

I am designing a module that has to run at 350MHz. I am in the
architecture phase and would like to know how to figure out the
possible frequency of operation of the design before entering the
synthesis phase. Normally we have to wait till the synthesis to get an
idea about the frequency of operation. I need a rough idea with 10-15%
error margin.

What if the frequecncy fails to meet the requrement and the difference
is very big and cannot be solved in the RTL optimization or syntheis
techniques. This amounts to again visiting the High level design to
figure out the bottlenecks .

I am interested in the techniques to find the rough idea of the
frequency of operation in the early phase of the design to meet the
frequency of demand if it is high speed design .

Secondly how to get a rough idea about the no of flops in the design
before entering the synthesis phase.

sharing any handout or methodology followed will be highly
appreciated.

THanks

Vips

 

[Martin Thompson]

Vips <thevipulsinha@gmail.com> writes:

Hello All ,

I am designing a module that has to run at 350MHz. I am in the
architecture phase and would like to know how to figure out the
possible frequency of operation of the design before entering the
synthesis phase. Normally we have to wait till the synthesis to get an
idea about the frequency of operation. I need a rough idea with 10-15%
error margin.

What FPGA family are you targetting? Is your application amenable to
pipelining? Have you done anything similar before? How much of it is
going to be dominated by the LUT timing, how much by the DSP/RAM blocks?

If you know what you are doing, and it's not too different a task to
previous ones, you might get within 15% without writing any code. If
not, I'd be tempted to hire someone that does have that experience to do
you a design study.

What if the frequecncy fails to meet the requrement and the difference
is very big and cannot be solved in the RTL optimization or syntheis
techniques. This amounts to again visiting the High level design to
figure out the bottlenecks .

Yes, that's life. Do the work up front if you already know enough, or
do enough work to learn enough. Then you'll know.

I am interested in the techniques to find the rough idea of the
frequency of operation in the early phase of the design to meet the
frequency of demand if it is high speed design .

Secondly how to get a rough idea about the no of flops in the design
before entering the synthesis phase.

Not usually an issue, unless (as someone else said recently) you're Ray
Andraka I always run out of LUTs first.

Again estimations can be done by one skilled in the art, but the
accuracy depends on how well you understand what you are going to be
implementing.

sharing any handout or methodology followed will be highly
appreciated.

I think the best methodology (unless I'm seriously misreading your/you
employers existing capabilities) is to get some help in. (And that's not a
pitch for work, I have plenty on already I'm afraid!)

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

 

[SCOTTY9000]

The xilinx documentation has got helpful tables in giving information abou
fmax for various structures such as BRAM, CAM etc.



---------------------------------------
Posted through http://www.FPGARelated.com

 

[Tim Wescott]

On Mon, 19 Mar 2012 09:41:49 +0000, Martin Thompson wrote:

Vips <thevipulsinha@gmail.com> writes:

Hello All ,

I am designing a module that has to run at 350MHz. I am in the
architecture phase and would like to know how to figure out the
possible frequency of operation of the design before entering the
synthesis phase. Normally we have to wait till the synthesis to get an
idea about the frequency of operation. I need a rough idea with 10-15%
error margin.

What FPGA family are you targetting? Is your application amenable to
pipelining? Have you done anything similar before? How much of it is
going to be dominated by the LUT timing, how much by the DSP/RAM blocks?

If you know what you are doing, and it's not too different a task to
previous ones, you might get within 15% without writing any code. If
not, I'd be tempted to hire someone that does have that experience to do
you a design study.


What if the frequecncy fails to meet the requrement and the difference
is very big and cannot be solved in the RTL optimization or syntheis
techniques. This amounts to again visiting the High level design to
figure out the bottlenecks .

Yes, that's life. Do the work up front if you already know enough, or
do enough work to learn enough. Then you'll know.


I am interested in the techniques to find the rough idea of the
frequency of operation in the early phase of the design to meet the
frequency of demand if it is high speed design .

Secondly how to get a rough idea about the no of flops in the design
before entering the synthesis phase.

Not usually an issue, unless (as someone else said recently) you're Ray
Andraka I always run out of LUTs first.

Again estimations can be done by one skilled in the art, but the
accuracy depends on how well you understand what you are going to be
implementing.


sharing any handout or methodology followed will be highly appreciated.

I think the best methodology (unless I'm seriously misreading your/you
employers existing capabilities) is to get some help in. (And that's
not a pitch for work, I have plenty on already I'm afraid!)

You can also prototype the parts that you know, from experience, to be
bottlenecks -- but without experience, you can't tell the bottlenecks.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com