Watchdog reset for fpga designs

[nba83]

hi
i 'm designing a board with fpga spartan 3(Industrial series) . whil
testing the board, specially when there is spike on any input pin of fpga
fpga enters unknown sate and won't do its job correctly, but after reset i
continues working. is it a common design practice to have an externa
watchdog timer to reset the fpga in fpga based boards in case it is i
unknown state, like watchdog timer in microcontrollers? I thought tha
fpgas are more stable than microcontroller in response to noise, but in m
test design I experienced the same thing similar to microcontrollers.
are gates in fpga altered due to noise??
tnx in advanced for any comment

---------------------------------------
Posted through http://www.FPGARelated.com

 

[Andy Bartlett]

"nba83" <nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote in message
news:F5udnToY5aAKceLSnZ2dnUVZ_rSdnZ2d@giganews.com...

hi
i 'm designing a board with fpga spartan 3(Industrial series) . while
testing the board, specially when there is spike on any input pin of fpga,
fpga enters unknown sate and won't do its job correctly, but after reset
it
continues working. is it a common design practice to have an external
watchdog timer to reset the fpga in fpga based boards in case it is in
unknown state, like watchdog timer in microcontrollers? I thought that
fpgas are more stable than microcontroller in response to noise, but in my
test design I experienced the same thing similar to microcontrollers.
are gates in fpga altered due to noise??
tnx in advanced for any comment

---------------------------------------
Posted through http://www.FPGARelated.com

Never known an FPGA (Altera) to crash in over 25 years. Maybe your PSU volts
are suspect.
I always enable the FPGA CRC checking which will cause the device to
'reboot' from external memory if the internally calculated CRC ever differs
from the CRC supplied during loading.
Maybe Xilinx do not have this feature?

Andy

 

[Tim Wescott]

On Sat, 07 Apr 2012 02:28:23 -0500, nba83 wrote:

hi
i 'm designing a board with fpga spartan 3(Industrial series) . while
testing the board, specially when there is spike on any input pin of
fpga, fpga enters unknown sate and won't do its job correctly, but after
reset it continues working. is it a common design practice to have an
external watchdog timer to reset the fpga in fpga based boards in case
it is in unknown state, like watchdog timer in microcontrollers? I
thought that fpgas are more stable than microcontroller in response to
noise, but in my test design I experienced the same thing similar to
microcontrollers. are gates in fpga altered due to noise?? tnx in
advanced for any comment

--------------------------------------- Posted through
http://www.FPGARelated.com

Define "spike" -- do you mean a runt pulse, or do you mean an overvoltage
spike?

The FPGA designers that I work with personally are sensitive to their
designs locking up or otherwise getting wedged in illegal states, and
have a plethora of design measures to prevent that from happening.

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

 

On Saturday, April 7, 2012 3:28:23 AM UTC-4, nba83 wrote:

hi
i 'm designing a board with fpga spartan 3(Industrial series) . while
testing the board, specially when there is spike on any input pin of fpga,
fpga enters unknown sate and won't do its job correctly, but after reset it
continues working. is it a common design practice to have an external
watchdog timer to reset the fpga in fpga based boards in case it is in
unknown state, like watchdog timer in microcontrollers? I thought that
fpgas are more stable than microcontroller in response to noise, but in my
test design I experienced the same thing similar to microcontrollers.
are gates in fpga altered due to noise??
tnx in advanced for any comment

By "reset" do you mean a re-programming/configuration of the FPGA, or a reset of the already configured logic?

I'm guessing that you mean the latter, and that the internal logice (a state machine, perhaps) is getting into an illegal state. Further guessing that a short pulse/spike is being seen by some FFs, but not all of those to which it fans out to. I.E. metastability through lack of proper synchronisation of the incoming signal.

As Tim says ther are a number of techniques used to avoid these kinds of problems, depending on the nature of the logic and the degree of resilience required. A first line of defence is to register all inputs with the FFs clocked by the same clock as used by the logic that it feeds, better still is two cascaded FFs.

Careful design of the state machines themselves is also important, e.g. trapping illegal states and transitioning to a legal one (usually the reset or initial state).

Without the specifics of your case it is difficult to give a more specific solution, but I hope that we have pointed you in the right direction.

--
Andy McC

 

[John Adair]

How large is your spike. If it exceeds something like 4.6V then you
are exceeding the specification of the device and all sorts of strange
things might happen. Which variety of Spartan-3 do you have 3, 3E or
3A?

Also look at the state machine reasoning mentioned elsewhere in the
post responses. Spartan-3 flip-flops etc. can respond to very narrow
glitches and you cannot rely on those being ignored by the device. In
this sphere some flip-flops might respond to a spike and others not so
state machines can go into funny illegal states and so on.

John Adair
Enterpoint Ltd. - Home of free PCIe seminars and labs.

On Apr 7, 8:28 am, "nba83"
<nba_baheri@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:

hi
i 'm designing a board with fpga spartan 3(Industrial series) . while
testing the board, specially when there is spike on any input pin of fpga,
fpga enters unknown sate and won't do its job correctly, but after reset it
continues working. is it a common design practice to have an external
watchdog timer to reset the fpga in fpga based boards in case it is in
unknown state, like watchdog timer in microcontrollers? I thought that
fpgas are more stable than microcontroller in response to noise, but in my
test design I experienced the same thing similar to microcontrollers.
are gates in fpga altered due to noise??
tnx in advanced for any comment

---------------------------------------
Posted throughhttp://www.FPGARelated.com