warnings when synthesizing

[rekz]

I have the code below:

http://pastie.org/929852

whenever I tried to synthesize it, it always says that :

One or more signals are missing in the sensitivity list of always
block. I think this is because I am not including instructMem into the
sensitivity list... but I don't think that's what I wan't. So is there
a workaround towards this warning?

and it says that instructMem is partially initialized... is there a
way to initialize the rest that I am not initializing? I know that I
have several off spots

 

On Apr 22, 11:40 am, rekz <aditya15...@gmail.com> wrote:

I have the code below:

http://pastie.org/929852

whenever I tried to synthesize it, it always says that :

One or more signals are missing in the sensitivity list of always
block. I think this is because I am not including instructMem into the
sensitivity list... but I don't think that's what I wan't. So is there
a workaround towards this warning?

If it is supposed to be a RAM, then your always block should react
when
the contents change. If it is supposed to be a ROM, then it should
never
change so it doesn't matter.

You cannot explicitly put an entire memory into an event control in
Verilog. You could use @(instructMem[Address]), which even avoids
executing when the address changes to another word with the same
value.
The repetition starts looking rather silly though, which should make
you
realize that you could have made ReadData a net and done a continuous
assignment to it instead of this verbose combinational always block.

Using the Verilog-2001 @* construct should ensure that your event
control
is complete. The LRM doesn't actually specify what happens if this
would
add an entire memory to the event control (which would be invalid),
but
most tools probably handle this as you would want.

 

[rekz]

On Apr 22, 2:12 pm, sh...@cadence.com wrote:

On Apr 22, 11:40 am, rekz <aditya15...@gmail.com> wrote:

I have the code below:

http://pastie.org/929852

whenever I tried to synthesize it, it always says that :

One or more signals are missing in the sensitivity list of always
block. I think this is because I am not including instructMem into the
sensitivity list... but I don't think that's what I wan't. So is there
a workaround towards this warning?

If it is supposed to be a RAM, then your always block should react
when
the contents change.  If it is supposed to be a ROM, then it should
never
change so it doesn't matter.

You cannot explicitly put an entire memory into an event control in
Verilog.  You could use @(instructMem[Address]), which even avoids
executing when the address changes to another word with the same
value.
The repetition starts looking rather silly though, which should make
you
realize that you could have made ReadData a net and done a continuous
assignment to it instead of this verbose combinational always block.

Using the Verilog-2001 @* construct should ensure that your event
control
is complete.  The LRM doesn't actually specify what happens if this
would
add an entire memory to the event control (which would be invalid),
but
most tools probably handle this as you would want.

Are you telling me that I should use assign? Problem is that when I
use assign in ReadData it won't synthesize
as well as using @* construct