warning: vcom-1186

[JK]

Hi,

I was trying example of Peter Ashenden VHDL book:

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;

entity full_adder is
port (
a, b, c_in : in bit;
c_out, sum : out bit
);
end entity full_adder;

architecture truth_table of full_adder is
begin

with bit_vector'(a, b, c_in) select
(c_out, sum) <= bit_vector'("00") when "000",
bit_vector'("01") when "001",
bit_vector'("01") when "010",
bit_vector'("10") when "011",
bit_vector'("01") when "100",
bit_vector'("10") when "101",
bit_vector'("10") when "110",
bit_vector'("11") when "111";

end architecture truth_table;

vcom -2002 -explicit -work practice full_adder.vhd
#Model Technology Modelsim SE vcom 6.3 Compiler 2007.05 May 4 2007
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity full_adder
# -- Compiling architecture truth_table of full_adder
# ** Warning: full_adder.vhd(15): (vcom-1186) Array type selected
signal assignment expression must be of a locally static subtype.


Why warning??? What does this locally static subtype mean??

Regards,
JK