Warning on DCM min frequency...

[Kelvin]

Hi, there:

I am using a Virtex-2's DCM to convert a 40MHz clock into synchronized 12MHz
(40X3/10) and 4MHz
(40/10) clocks.

In the attributes I set these constrainsts...Simulation and synthesis were
correct. The min frequency
seems to be within the specification of DCM. but I don't want to see this
warning...What constraint do
I need to set? (Not the trick suppress the warning)

WARNING:Timing:2799 - The output clock clk_12m_rx from DCM DCM0 has a period
(frequency) specification of 83333 ps (12.00 Mhz). This violates the
maximum
period (minimum frequency) of 41670 ps (24.00 Mhz).



//synthesis translate_off
defparam .......................blah blah............................
//synthesis translate_on
// synthesis attribute CLKIN_PERIOD of DCM0 is 25
// synthesis attribute DLL_FREQUENCY_MODE of DCM0 is "LOW"
// synthesis attribute DUTY_CYCLE_CORRECTION of DCM0 is "TRUE"
// synthesis attribute STARTUP_WAIT of DCM0 is "TRUE"
// synthesis attribute DFS_FREQUENCY_MODE of DCM0 is "LOW"
// synthesis attribute CLKDV_DIVIDE of DCM0 is 10
// synthesis attribute CLKFX_DIVIDE of DCM0 is 10
// synthesis attribute CLKFX_MULTIPLY of DCM0 is 3
// synthesis attribute CLK_FEEDBACK of DCM0 is "1X"
// synthesis attribute CLKOUT_PHASE_SHIFT of DCM0 is "FIXED"
// synthesis attribute PHASE_SHIFT of DCM0 is 0



Best Regards,
Kelvin

 

[Austin Lesea]

Kelvin,

The CLKFX output can not go below 24 MHz. If you do not use CLKFX, and
are using CLKDV, then do not set M, or D, and do not use (instantiate)
the CLKFX output, and the software will not error out.

Austin

Kelvin wrote:

Hi, there:

I am using a Virtex-2's DCM to convert a 40MHz clock into synchronized 12MHz
(40X3/10) and 4MHz
(40/10) clocks.

In the attributes I set these constrainsts...Simulation and synthesis were
correct. The min frequency
seems to be within the specification of DCM. but I don't want to see this
warning...What constraint do
I need to set? (Not the trick suppress the warning)

WARNING:Timing:2799 - The output clock clk_12m_rx from DCM DCM0 has a period
(frequency) specification of 83333 ps (12.00 Mhz). This violates the
maximum
period (minimum frequency) of 41670 ps (24.00 Mhz).



//synthesis translate_off
defparam .......................blah blah............................
//synthesis translate_on
// synthesis attribute CLKIN_PERIOD of DCM0 is 25
// synthesis attribute DLL_FREQUENCY_MODE of DCM0 is "LOW"
// synthesis attribute DUTY_CYCLE_CORRECTION of DCM0 is "TRUE"
// synthesis attribute STARTUP_WAIT of DCM0 is "TRUE"
// synthesis attribute DFS_FREQUENCY_MODE of DCM0 is "LOW"
// synthesis attribute CLKDV_DIVIDE of DCM0 is 10
// synthesis attribute CLKFX_DIVIDE of DCM0 is 10
// synthesis attribute CLKFX_MULTIPLY of DCM0 is 3
// synthesis attribute CLK_FEEDBACK of DCM0 is "1X"
// synthesis attribute CLKOUT_PHASE_SHIFT of DCM0 is "FIXED"
// synthesis attribute PHASE_SHIFT of DCM0 is 0



Best Regards,
Kelvin