Warning of testbench in Verilog

I was writting a little testbench for my verilog module in verilog.
The module under test is

module test1 ( clock_in, data_in, data_out );
input clock_in;
input [31:0] data_in;
output [31:0] data_out;

The testbench is

module Test_test1;
wire [31:0] data_out;
reg [31:0] data_in;
reg clock_in;
test1 u1(clock_in,data_in,data_out);
initial begin
clock_in=1;
data_in=32'HAAAAAAAA;
end
$display(" clock_in=%b data_in=%h data_out=%h
",clock_in,data_in,data_out);
endmodule

The problem is when I was trying to simulate it under modelsim, I got
warning like

** Warning: (vsim-3015) /home/elyl3/examples_f/addone/testbench.v(5):
[PCDPC] - Port size (32 or 32) does not match connection size (1) for
port 'data_in'.
Region: /test1_tb/u1
** Warning: (vsim-3015) /home/elyl3/examples_f/addone/testbench.v(5):
[PCDPC] - Port size (32 or 32) does not match connection size (1) for
port 'data_out'.
Region: /test1_tb/u1

Have no ideas why I cann't assign a 32bits value to my module port?
very confused.
Any tips will be appreciated.

Thanks a lot

Andy

 

[gongguowang@yahoo.com]

signals width mismatch, please check your signals which produce
warnings

jiou0962@gmail.com wrote:

I was writting a little testbench for my verilog module in verilog.
The module under test is

module test1 ( clock_in, data_in, data_out );
input clock_in;
input [31:0] data_in;
output [31:0] data_out;

The testbench is

module Test_test1;
wire [31:0] data_out;
reg [31:0] data_in;
reg clock_in;
test1 u1(clock_in,data_in,data_out);
initial begin
clock_in=1;
data_in=32'HAAAAAAAA;
end
$display(" clock_in=%b data_in=%h data_out=%h
",clock_in,data_in,data_out);
endmodule

The problem is when I was trying to simulate it under modelsim, I got
warning like

** Warning: (vsim-3015) /home/elyl3/examples_f/addone/testbench.v(5):
[PCDPC] - Port size (32 or 32) does not match connection size (1) for
port 'data_in'.
Region: /test1_tb/u1
** Warning: (vsim-3015) /home/elyl3/examples_f/addone/testbench.v(5):
[PCDPC] - Port size (32 or 32) does not match connection size (1) for
port 'data_out'.
Region: /test1_tb/u1

Have no ideas why I cann't assign a 32bits value to my module port?
very confused.
Any tips will be appreciated.

Thanks a lot

Andy

 

the problem is these the width of these two signal is same, so I have
no idea where this warning from ?

 

[Jason Rosinski]

Hmm, looks like it should be okay. The only thing I would suggest would be to check the port
order, since it looks like your using positional connections as opposed to named. Maybe see if
making the connections to u1 named makes any difference... Other than that I have no idea <G>.

jiou0962@gmail.com wrote:

I was writting a little testbench for my verilog module in verilog.
The module under test is

module test1 ( clock_in, data_in, data_out );
input clock_in;
input [31:0] data_in;
output [31:0] data_out;

The testbench is

module Test_test1;
wire [31:0] data_out;
reg [31:0] data_in;
reg clock_in;
test1 u1(clock_in,data_in,data_out);
initial begin
clock_in=1;
data_in=32'HAAAAAAAA;
end
$display(" clock_in=%b data_in=%h data_out=%h
",clock_in,data_in,data_out);
endmodule

The problem is when I was trying to simulate it under modelsim, I got
warning like

** Warning: (vsim-3015) /home/elyl3/examples_f/addone/testbench.v(5):
[PCDPC] - Port size (32 or 32) does not match connection size (1) for
port 'data_in'.
Region: /test1_tb/u1
** Warning: (vsim-3015) /home/elyl3/examples_f/addone/testbench.v(5):
[PCDPC] - Port size (32 or 32) does not match connection size (1) for
port 'data_out'.
Region: /test1_tb/u1

Have no ideas why I cann't assign a 32bits value to my module port?
very confused.
Any tips will be appreciated.

Thanks a lot

Andy

 

[Jason Zheng]

jiou0962@gmail.com wrote:

the problem is these the width of these two signal is same, so I have
no idea where this warning from ?

The best practice to prevent any mistakes is to use explicit

instantiation. It's a little extra to write, but I'm sure 99% of the
folks here agree with me, explicit instantiation will save you a lot of
time in checking the port orders in the long run. There are many
automation tools that even do this automatically for you, such as emacs
with verilog-mode.