warning in synthesis

[srinukasam]

hello
in my design i need a conversion from bit_vector to integer for that i
wrote my own function.
in that function i initialized two integer variables with zero(0).
while doing synthesis with synopsys..its giving warning like this..

Warning: Initial values for signals are not supported for synthesis. They
are ignored on line 35 (VHDL-2022)

if i not initialze the variables its giving error at the simulation time.

my idea( but i dont know weather it works r not thats why iam asking u )
converting bitbector to std_ulogic then converting to integer using
CONV_INTEGER function thats already available in library.
but how can i convert bit_vector to std_ulogic_vector .

or do suggest any other alternate solution.
please giude me
thank you

 

[Mike Treseler]

srinukasam wrote:

in my design i need a conversion from bit_vector to integer for that i
wrote my own function.

use ieee.numeric_bit.all ;
.... my_nat := to_integer(unsigned(my_bitvector);
-- or
.... my_int := to_integer(signed(my_bitvector);

-- Mike Treseler

 

if i not initialze the variables its giving error at the simulation time.
Probably, you can write a testbench here. or else follow the solution

given below.

or do suggest any other alternate solution.
If an internal signal in your design necessarily requires an

initialization, you can include a preset signal in your entity, which
should be a pulse in the beginning. Whenever it is high, set all the
signals to their initialized values. In the meantime, don't perform any
operation required for generating the output (or force output as
zeros). When the pulse is low, perform the routine operations. You can
generate preset pulse yourself also, if you don't want it to be an
input to your entity. A sample template can be as follows:

process (preset, clock)
begin
if (preset = '1') then
signal1 <= init_value;
signal2 <= init_value;
---------
---------
output <= (others => '0');
elsif (clock = '1' and clock'event) then
output <= valid_value;
end if;

=========This is synthesizable as well.

KVM.