Warning in Modelsim - vector truncated

Hi,

I am using the following conversion in my code:

--------------------------------------
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

begin
....
ls_rom_rdaddress <std_logic_vector(to_unsigned(ls_rom_rdaddress_count, 6));

....
end;

When starting my functional simulation in Modelsim I get the following
warning:

Time: 122565394 ps Iteration: 4 Instance:
/tb_pattern_sequencer/uut1/i_tests
# ** Warning: NUMERIC_STD.TO_UNSIGNED: vector truncated

Can someone explain ?

Thank you for your help.

Rgds
André

 

signal ls_rom_rdaddress : std_logic_vector(5 downto 0);
signal ls_rom_rdaddress_count : integer range 0 to 64;


I need the range to go up to 64 to check some condition which has
nothing to do with the ROM read address (which goes up to 63).

Is that truncation a problem ?

 

[Duane Clark]

ALuPin@web.de wrote:

Hi,

I am using the following conversion in my code:

--------------------------------------
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

begin
...
ls_rom_rdaddress <=
std_logic_vector(to_unsigned(ls_rom_rdaddress_count, 6));

...
end;

When starting my functional simulation in Modelsim I get the following
warning:

Time: 122565394 ps Iteration: 4 Instance:
/tb_pattern_sequencer/uut1/i_tests
# ** Warning: NUMERIC_STD.TO_UNSIGNED: vector truncated

Can someone explain ?

The warnings only come about when the input number is negative. I would
like to see a better solution, but to eliminate the warnings, I did this:
if int_v < 0 then
coeff_data := std_logic_vector(to_unsigned(int_v+65536, 16));
else
coeff_data := std_logic_vector(to_unsigned(int_v, 16));
end if;
Fortunately, I was only using that in a testbench, so I was not
concerned with how it would synthesize.