Warning: Global clock buffer not inserted on net rtlc1n42

[Ahmed Samieh]

hi all,

what is the problem with using signal in different processes?
like

for signal en

p1 : process(clk,en,....)
begin
if (rising_edge(clk) and en = '1') then
....
end if;
end process p1;

p2 : process(en, ...)
begin
if rising_edge(en) then
....
end if;
end process p2;

simulation work fine, synthesize produce this warning

Warning: Global clock buffer not inserted on net rtlc1n42

what is this warning? and how to avoide such a warning?

thanx,

Ahmed Samieh

 

[Ralf Hildebrandt]

Ahmed Samieh schrieb:

what is the problem with using signal in different processes?
like

for signal en

p1 : process(clk,en,....)
begin
if (rising_edge(clk) and en = '1') then
....
end if;
end process p1;

You probably want

p1 : process(clk)
if rising_edge(clk) then
if (en='1') then
....
end if;
end if;
end process p1;

If you add the en signal to the if clause as you do, this results in a
clock gate. (AFAIK)
If you put it inside the synchronous test, it is just a selector for a
multiplexer in front of some flipflops.

p2 : process(en, ...)
begin
if rising_edge(en) then
....
end if;
end process p2;

This should be no problem.
(You only need en in the sensitivity list.)

simulation work fine, synthesize produce this warning

Warning: Global clock buffer not inserted on net rtlc1n42

Some synthesis libraries (some FPGAs) do not support global clock
buffers for signals, that are fed into combinational logic.

Ralf

 

[Ahmed Samieh]

On Jun 6, 9:32 pm, Ralf Hildebrandt <Ralf-Hildebra...@gmx.de> wrote:

Ahmed Samieh schrieb:

what is the problem with using signal in different processes?
like

for signal en

p1 : process(clk,en,....)
begin
if (rising_edge(clk) and en = '1') then
....
end if;
end process p1;

You probably want

p1 : process(clk)
if rising_edge(clk) then
if (en='1') then
....
end if;
end if;
end process p1;

If you add the en signal to the if clause as you do, this results in a
clock gate. (AFAIK)
If you put it inside the synchronous test, it is just a selector for a
multiplexer in front of some flipflops.

p2 : process(en, ...)
begin
if rising_edge(en) then
....
end if;
end process p2;

This should be no problem.
(You only need en in the sensitivity list.)

simulation work fine, synthesize produce this warning

Warning: Global clock buffer not inserted on net rtlc1n42

Some synthesis libraries (some FPGAs) do not support global clock
buffers for signals, that are fed into combinational logic.

Ralf

thanx Ralf,
i changed the FPGA and the warning had gone
but, i the question still, what is the reason of this global clock
buffer ....
while another 2 processes like :

p1 : process(clk,...)
begin
if rising_edge(clk) then
....
end if;
end process p1;
p2 : process(clk,...)
begin
if falling_edge(clk) then
....
end if;
end process p1;

will not resulte the warning of global clock buffer !!

is there any explanation ?

thanx

Ahmed Samieh

 

[Ralf Hildebrandt]

Ahmed Samieh schrieb:

but, i the question still, what is the reason of this global clock
buffer ....
while another 2 processes like :

p1 : process(clk,...)
begin
if rising_edge(clk) then
....
end if;
end process p1;
p2 : process(clk,...)
begin
if falling_edge(clk) then
....
end if;
end process p1;

will not resulte the warning of global clock buffer !!

is there any explanation ?

A global clock buffer is a special strong driver for a clock. The clock
is routed via special clock wires. It is not fed into the normal logic
wires of the FPGA. This reduces clock skew to a minimum.

You can't just make a hook to this global clock wire and use this global
wherever you want. The global clock is routed to the clk-Input of any
Flipflop (better: to a multiplexer in front of this clk-Input).
Therefore you can use the global clock with every flipflop (rising_edge
/ falling_edge). But it is often (depending on the FPGA) impossible to
use this global clock as an input to combinational logic.

If you use the clock inside combinational logic, the clock can't be
routed via the global net and has to be routed via a normal logic net.
Because this results in a lot of skew the routing tool will output a
warning.

Ralf

 

[Ahmed Samieh]

On Jun 7, 8:16 pm, Ralf Hildebrandt <Ralf-Hildebra...@gmx.de> wrote:

A global clock buffer is a special strong driver for a clock. The clock
is routed via special clock wires. It is not fed into the normal logic
wires of the FPGA. This reduces clock skew to a minimum.

You can't just make a hook to this global clock wire and use this global
wherever you want. The global clock is routed to the clk-Input of any
Flipflop (better: to a multiplexer in front of this clk-Input).
Therefore you can use the global clock with every flipflop (rising_edge
/ falling_edge). But it is often (depending on the FPGA) impossible to
use this global clock as an input to combinational logic.

If you use the clock inside combinational logic, the clock can't be
routed via the global net and has to be routed via a normal logic net.
Because this results in a lot of skew the routing tool will output a
warning.

Ralf- Hide quoted text -

- Show quoted text -

thanx Ralf for your help
i found this paper
http://www.ece.gatech.edu/academic/courses/fpga/Xilinx/downloads/lab3.pdf

Ahmed Samieh