want info on resolved signal....

[Vineeth V]

hi
i want to reset all the signals,variables etc that i have used in
the code so that after the o/p for a
particular i/p is observed the s/m is reset so that it can accept
further i/p..so i planned to use a separate process for this resetting
purpose.i gave the "o/p obtained" condition in the sensitivity list...
but i got an error message about resolved signals...the problem is
with the signals that i declared as integers...nothing wrong with
other signals...pls help me

or else can u suggest me some other better way for
resetting all signals n variables that i have used in the code......

 

[KJ]

"Vineeth V" <vineeth_aries@rediffmail.com> wrote in message
news:1172573331.783104.29180@k78g2000cwa.googlegroups.com...

hi
i want to reset all the signals,variables etc that i have used in
the code so that after the o/p for a
particular i/p is observed the s/m is reset so that it can accept
further i/p..so i planned to use a separate process for this resetting
purpose.i gave the "o/p obtained" condition in the sensitivity list...
but i got an error message about resolved signals...the problem is
with the signals that i declared as integers...nothing wrong with
other signals...pls help me

or else can u suggest me some other better way for
resetting all signals n variables that i have used in the code......

Not a clue what "i/p", "o/p" or "s/m" is about.....but anyway, any signal

must basically originate from a single process unless it is a type that can
specifically come from more than one (example std_logic). However, even
though things like std_logic 'can' be driven by more than one process, the
only way you can do this is to specify just exactly when a particular
process can be driving it....otherwise you get unknowns since it is likely
that the two processes are trying to drive them to different states.

The bottom line is that you need to rewrite your code so that each signal
comes out of a single process instead of trying to have some separate
process 'reset everything'..

Example
process(Clock)
begin
if rising_edge(Clock) then
if (reset = '1') then
My_Sig <= '0';
else
-- Put your logic for My_Sig in here
end if;
end process;

You can put as many signals as you want inside one process (i.e. My_Sig1,
My_Sig2, My_Sig3, etc.) the important thing is that you can not have two
processes each with an equation for 'My_Sig'.

The reason you're only seeing it as a problem with your integers is because
integers are not a resolved type (i.e. by definition, they can not have more
than one driver) so when the compiler detects this it immediately fails.
Your other signals are probably std_logic types which can have multiple
drivers so the compiler doesn't complain but if you could simulate you'd
probably find that all of your std_logic signals are always 'X' and then
have to debug down to why that is. That's why it's better to use std_ulogic
since the compiler will again immediately complain (like it is doing for you
with type 'integer') about having more than one process driving a signal of
that type.

Good luck

Kevin Jennings

 

[Colin Paul Gloster]

In news:eLUEh.2278$jx3.1392@newssvr25.news.prodigy.net timestamped
Tue, 27 Feb 2007 11:38:50 GMT, "KJ" <kkjennings@sbcglobal.net> posted:
""Vineeth V" <vineeth_aries@rediffmail.com> wrote in message
news:1172573331.783104.29180@k78g2000cwa.googlegroups.com...

hi
i want to reset all the signals,variables etc that i have used in
the code so that after the o/p for a
particular i/p is observed the s/m is reset so that it can accept
further i/p[..]
[..]

Not a clue what "i/p", "o/p" or "s/m" is about"

Possiply input; output; and state machine respectively, but I would
prefer that people use terms which mean something instead of scarcely
intelligible abbreviations.


"[..]

The reason you're only seeing it as a problem with your integers is because
integers are not a resolved type (i.e. by definition, they can not have more
than one driver) so when the compiler detects this it immediately fails.
Your other signals are probably std_logic types which can have multiple
drivers so the compiler doesn't complain but if you could simulate you'd
probably find that all of your std_logic signals are always 'X' and then
have to debug down to why that is. That's why it's better to use std_ulogic
since the compiler will again immediately complain (like it is doing for you
with type 'integer') about having more than one process driving a signal of
that type."


I like this advice to prefer std_ulogic instead of std_logic, but
unfortunately the official policy here is to prefer std_logic instead
of std_ulogic.

Regards,
Colin Paul Gloster

 

[KJ]

I like this advice to prefer std_ulogic instead of std_logic, but
unfortunately the official policy here is to prefer std_logic instead
of std_ulogic.

There is some value to standardizing on a 'single' data type, but like
everything there is a cost. The price you pay is the human time that
you'll spend debugging down to the cause of an 'X' being multiple
drivers. Assuming that the simulation tools have already been
purchased, then there is no incremental cost by using the tools to
find these multiple drivers. Might want to point that out to the
'policy makers' to see if it make a difference.

Rather than fighting the policy makers, another technique is to simply
run the code through synthesis even if you're only in the design/
simulation stage. Synthesis tools don't cotton to multiple drivers on
a net either and will error out. Saves you the debug effort to find
them in simulation although typically synthesis stops after the first
such multiple driver situation so you have to keep on trying until it
makes it through. It's a bit of a pain, but the synthesis task can be
run as a background task while you're still working on the design and
sim. View this as using the synthesis tool as giving you feedback on
your design as it stands, not as something that has to complete before
you can move on.

Kevin Jennings

 

[Mike Treseler]

Vineeth V wrote:

i want to reset all the signals,variables etc
....
i planned to use a separate process for this resetting
purpose.
can u suggest me some other better way for
resetting all signals n variables that i have used in the code......

In a single process entity, I can reset
all the variables in a single procedure
and no signal declarations are required.

See the procedure "init_regs"
in the design examples here:

http://home.comcast.net/~mike_treseler/

-- Mike Treseler