Want flag to keep value through all states

[Shannon]

I am using a single-process state-machine style of coding. I have a
flag that gets set or cleared in one state. I want it to keep
whatever value that is throughout the rest of the state machine until
the machine returns to that state. What is the correct way of doing
this?

Please note that I am not referring to a "default" state. That much I
understand. I just want the flag to be set once and then stay that
way regardless of the condition that set it changing later.

Process (clk)
begin
if rising_edge(clk) then
case state
when one =>
flag <= input;
...
when two =>
if flag = '1' then
....
else
....
etc...

Thanks,
Shannon

 

[Shannon]

On Jun 15, 1:34 pm, Shannon <sgo...@sbcglobal.net> wrote:

I am using a single-process state-machine style of coding.  I have a
flag that gets set or cleared in one state.  I want it to keep
whatever value that is throughout the rest of the state machine until
the machine returns to that state.  What is the correct way of doing
this?

Please note that I am not referring to a "default" state.  That much I
understand.  I just want the flag to be set once and then stay that
way regardless of the condition that set it changing later.

Process (clk)
begin
  if rising_edge(clk) then
    case state
      when one =
         flag <= input;
         ...
      when two =
         if flag = '1' then
          ....
         else
         ....
etc...

Thanks,
Shannon

I'm suffering post traumatic "send" disorder....

I'm betting that I don't have to do anything since it is in a clocked
process and will become a register.

Shannon

 

[Dave]

On Jun 15, 4:34 pm, Shannon <sgo...@sbcglobal.net> wrote:

I am using a single-process state-machine style of coding.  I have a
flag that gets set or cleared in one state.  I want it to keep
whatever value that is throughout the rest of the state machine until
the machine returns to that state.  What is the correct way of doing
this?

Please note that I am not referring to a "default" state.  That much I
understand.  I just want the flag to be set once and then stay that
way regardless of the condition that set it changing later.

Process (clk)
begin
  if rising_edge(clk) then
    case state
      when one =
         flag <= input;
         ...
      when two =
         if flag = '1' then
          ....
         else
         ....
etc...

Thanks,
Shannon

If you simply don't assign the signal's value in those states where
the signal should remain unchanged, then the value will remain the
same until the next clock tick. The synthesizer will implement this by
making the clock enable for the signal's register '0' for those states
where the signal is not assigned. This is one of the nice things about
single-process state machines.

Dave