wait states

I am in need of understanding the importance of WAIT states in an
state machine diagram ? What are the implications and ramifications of
this daunting STATE that basically does nothing ?

 

[Ralf Hildebrandt]

cali_playa_4_life@yahoo.com schrieb:

I am in need of understanding the importance of WAIT states in an
state machine diagram ? What are the implications and ramifications of
this daunting STATE that basically does nothing ?

wait != nothing

Usually you use a state machine to control a component. If this
component requires the control signals to stay unchanged for a certain
period of time you have to wait until this time has passed. E.g. for
writing to an EERPOM you have to wait some ms while the programming
takes place.

Ralf