wait statement with Xilinx ise webpack4.2

[MarcoŠ]

Hi! I'm an engineer student and having some problems with xilinx ise webpack
4.2

I have to realize an interface module which waits for a signal from a
transmitter module before transferring the data from a bidirectional bus to
the tx module...the problem is that i couldn't synthesize it because the
compiler reports the following error:

ERROR:Xst:850 - "UART_control.v", line 42: Unsupported Wait Statement.

Here is the code:

always @(negedge NRD)
begin

wait (oktx);

i_readout <= 0;

wait (oktx);

i_res <= 1;
i_readout <= 1;

end


How could i realize the same function without the wait statement? I tried
with a while construct without success...

Thanks in advance to all

 

[Jim Wu]

How could i realize the same function without the wait statement? I tried
with a while construct without success...

"wait" statement is not synthesizable. Try to use a state machine.

jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips

 

[Andy Peters]

"MarcoŠ" <Seiryu.nospam@fastwebnet.it> wrote in message news:<IZBSb.16524$VS6.8853@tornado.fastwebnet.it>...

Hi! I'm an engineer student and having some problems with xilinx ise webpack
4.2

I have to realize an interface module which waits for a signal from a
transmitter module before transferring the data from a bidirectional bus to
the tx module...the problem is that i couldn't synthesize it because the
compiler reports the following error:

ERROR:Xst:850 - "UART_control.v", line 42: Unsupported Wait Statement.

Here is the code:

always @(negedge NRD)
begin

wait (oktx);

i_readout <= 0;

wait (oktx);

i_res <= 1;
i_readout <= 1;

end


How could i realize the same function without the wait statement? I tried
with a while construct without success...

RTFM. The synthesis manual has a section about "non-synthesizable
constructs."

Looks like you're trying to design something that looks for the
assertion of a read enable, and when the thing doing to the reading
grabs the data gets it, then you continue. Or something.

Unfortunately, you'll need to recode your logic. As the other poster
said, a state machine is a good thing. You might consider asking your
instructor to help you understand why your code is not correct. You
might further consider asking him to explain the "synthesizable
Verilog subset."

--a

 

[Sajan]

Try implementing the same using an "if" statement.
Things should work fine then.


"MarcoŠ" <Seiryu.nospam@fastwebnet.it> wrote in message news:<IZBSb.16524$VS6.8853@tornado.fastwebnet.it>...

Hi! I'm an engineer student and having some problems with xilinx ise webpack
4.2

I have to realize an interface module which waits for a signal from a
transmitter module before transferring the data from a bidirectional bus to
the tx module...the problem is that i couldn't synthesize it because the
compiler reports the following error:

ERROR:Xst:850 - "UART_control.v", line 42: Unsupported Wait Statement.

Here is the code:

always @(negedge NRD)
begin

wait (oktx);

i_readout <= 0;

wait (oktx);

i_res <= 1;
i_readout <= 1;

end


How could i realize the same function without the wait statement? I tried
with a while construct without success...

Thanks in advance to all