Wait statement error

S

Shannon

Guest
I'm starting to use ModelSim (the version included with Quartus II)
for my simulations. I've been a long time user of the waveform
simulator in Quartus but I thought I should stop using stone-knives
and bear-skins.

One problem I've hit early on: I have the following process in my
testbench:

DACclock : PROCESS
BEGIN
wait for 4 ns; DAC_clk <= not DAC_clk;
end PROCESS DACclock;

Seems pretty straightforward eh? ModelSim likes it and produces the
clock waveform that I would expect. Quartus however complains:

Error (10533): VHDL Wait Statement error at HighSpeedDACTB.vhd(72):
Wait Statement must contain condition clause with UNTIL keyword

Huh?

Shannon
 
On 25 Mar, 15:06, Shannon <sgo...@sbcglobal.net> wrote:
I'm starting to use ModelSim (the version included with Quartus II)
for my simulations.  I've been a long time user of the waveform
simulator in Quartus but I thought I should stop using stone-knives
and bear-skins.

One problem I've hit early on: I have the following process in my
testbench:

DACclock : PROCESS
BEGIN
   wait for 4 ns; DAC_clk  <= not DAC_clk;
end PROCESS DACclock;

Seems pretty straightforward eh?  ModelSim likes it and produces the
clock waveform that I would expect.  Quartus however complains:

Error (10533): VHDL Wait Statement error at HighSpeedDACTB.vhd(72):
Wait Statement must contain condition clause with UNTIL keyword

Huh?

Shannon
Click to expand...
Id raise it as an Issue with Altera, but given that they include
Modelsim AE, they'll probably just tell you to use that instead.
 
Shannon
Is this from the Quartus synthesis tool? You only need to
tell the synthesis tool about your design. There may be a
place to mark the file as a testbench file - make sure to
do this as synthesis tools don't like many things that are
part of the testbench.

Cheers,
Jim
SynthWorks VHDL Training
 
Shannon wrote:

It was from the "Analysis & Elaboration" tool. But I think I get the
picture now. When I tried to archive the whole project it said that
it had to do "Analysis & Elaboration" first. I just clicked on
"yes". I don't think it understands that it is a testbench project
and Elaboration is silly. (At least I think that is what is going on.)
Click to expand...
Quartus only knows about vhdl for *synthesis*.
Quartus cannot use vhdl code for simulation.
The quartus sim tool only knows about altera netlists and waveforms.
For a vhdl testbench, use modelsim.

-- Mike Treseler
 
On Mar 25, 8:33 am, JimLewis <j...@synthworks.com> wrote:
Shannon
Is this from the Quartus synthesis tool?  You only need to
tell the synthesis tool about your design.  There may be a
place to mark the file as a testbench file - make sure to
do this as synthesis tools don't like many things that are
part of the testbench.

Cheers,
Jim
SynthWorks VHDL Training
Click to expand...
It was from the "Analysis & Elaboration" tool. But I think I get the
picture now. When I tried to archive the whole project it said that
it had to do "Analysis & Elaboration" first. I just clicked on
"yes". I don't think it understands that it is a testbench project
and Elaboration is silly. (At least I think that is what is going on.)
 
Shannon wrote:

Next step is get get ModelSim to understand my memory initialization
file.
Click to expand...
I would make that a vhdl constant array.

-- Mike Treseler
 
On Mar 25, 10:00 am, Mike Treseler <mtrese...@gmail.com> wrote:
Shannon wrote:
It was from the "Analysis & Elaboration" tool.  But I think I get the
picture now.  When I tried to archive the whole project it said that
it had to do "Analysis & Elaboration" first.  I just clicked on
"yes".  I don't think it understands that it is a testbench project
and Elaboration is silly.  (At least I think that is what is going on..)

Quartus only knows about vhdl for *synthesis*.
Quartus cannot use vhdl code for simulation.
The quartus sim tool only knows about altera netlists and waveforms.
For a vhdl testbench, use modelsim.

     -- Mike Treseler
Click to expand...
Agreed.

Next step is get get ModelSim to understand my memory initialization
file.

Shannon
 
On Mar 25, 10:00 am, Mike Treseler <mtrese...@gmail.com> wrote:
Shannon wrote:
It was from the "Analysis & Elaboration" tool.  But I think I get the
picture now.  When I tried to archive the whole project it said that
it had to do "Analysis & Elaboration" first.  I just clicked on
"yes".  I don't think it understands that it is a testbench project
and Elaboration is silly.  (At least I think that is what is going on..)

Quartus only knows about vhdl for *synthesis*.
Quartus cannot use vhdl code for simulation.
The quartus sim tool only knows about altera netlists and waveforms.
For a vhdl testbench, use modelsim.

     -- Mike Treseler
Click to expand...
Agreed.

Next step is get get ModelSim to understand my memory initialization
file.

Shannon
 
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