Wait on...

[VHDL User]

Is there something that can be done with a WAIT ON statement that CANNOT
be done using a sensitivity list to a process other than allowing a
dynamic sensitivity (order of Wait statements in process)

 

[Allan Herriman]

On Thu, 26 Aug 2004 06:52:12 +0200, VHDL User
<supreet@phenix.rootshell.be> wrote:

Is there something that can be done with a WAIT ON statement that CANNOT
be done using a sensitivity list to a process other than allowing a
dynamic sensitivity (order of Wait statements in process)

For synthesisable code, no.

In simulation, yes, since you can say:

wait [on {SIGID,}] [until expr] [for time];

e.g.

wait until foo for 1 ns;

which gives you a timeout.

Regards,
Allan.

 

[Edmond Cote]

Allan Herriman wrote:

On Thu, 26 Aug 2004 06:52:12 +0200, VHDL User
supreet@phenix.rootshell.be> wrote:


Is there something that can be done with a WAIT ON statement that CANNOT
be done using a sensitivity list to a process other than allowing a
dynamic sensitivity (order of Wait statements in process)


For synthesisable code, no.

In simulation, yes, since you can say:

wait [on {SIGID,}] [until expr] [for time];

e.g.

wait until foo for 1 ns;

which gives you a timeout.

Regards,
Allan.

How about with behavioural synthesis tools?.. can anyone suggest any
good ones?

Thanks,

Ed