VSim component not bound

[Freaker85]

Hi,

I have a package with components in it, these components describe some
RAM-blocks (didnt wrote them myself, these were pre-defined and only
have these components, no architectures).

It compiles perfectly, when I run vsim it says
**Warning: (vsim-3473) Component 'ram' is not bound.
Time: 0 ns Iteration: 0 Region: /tv File: tv.vhd

I got other components in the same file, with these it has no problem
to bind... no warnings at all (these i wrote myself, with an
architecture and made some components from it)

help please,
Thank you

 

[KJ]

On Mar 13, 10:51 am, "Freaker85" <t_De_sm...@hotmail.com> wrote:

Hi,

I have a package with components in it, these components describe some
RAM-blocks (didnt wrote them myself, these were pre-defined and only
have these components, no architectures).

It compiles perfectly, when I run vsim it says
**Warning: (vsim-3473) Component 'ram' is not bound.
Time: 0 ns Iteration: 0 Region: /tv File: tv.vhd

I got other components in the same file, with these it has no problem
to bind... no warnings at all (these i wrote myself, with an
architecture and made some components from it)

help please,
Thank you

You need the entity/architectures of everything if you expect to
simulate. You need to get your hands on those entities and
architectures that "were pre-defined and only have these components,
no architectures)". Components don't simulate, entities and
architectures do.

Kevin Jennings

 

[Thomas Stanka]

On 13 Mrz., 15:51, "Freaker85" <t_De_sm...@hotmail.com> wrote:

I have a package with components in it, these components describe some
RAM-blocks (didnt wrote them myself, these were pre-defined and only
have these components, no architectures).

It compiles perfectly, when I run vsim it says
**Warning: (vsim-3473) Component 'ram' is not bound.
Time: 0 ns Iteration: 0 Region: /tv File: tv.vhd

I got other components in the same file, with these it has no problem
to bind... no warnings at all (these i wrote myself, with an
architecture and made some components from it)

You need to bound any "architecture" to this component. If you write
you own code, you would need the real architecture, entity and
preferably a configuration, that tells which architecture you like to
use for the entity for this instantiation.
It is of course possible to have verilog models or precompiled library
elements instead a architecture (like usually the primitive gates when
doing netlist simulations).
You can tell modelsim if it needs a dedicated configuration, or allow
modelsim to select a suitable component in the modelsim.ini.

I would first have a look, if you linked the library that contains
this RAM-Block.

bye Thomas