VPI Routines

I have the following heirarchy in verilog

top.v-----
|------A.v
|------B.v
|------C.v
|------D.v


Let us suppose I have vpi system function in D.v and the system
function needs the signal from A.v. Is it possible for me to use
vpi_handle_by_name() from module D.v go up the heirarchy into module
A.v to get the signal. I should be calling this vpi from D.v only.

Thanks
S

 

[Homuncilus]

I can't know what you meat

On 2ÔÂ3ČŐ, ÉĎÎç4Ęą43ˇÖ, sarma.nedun...@gmail.com wrote:

I have the following heirarchy in verilog

top.v-----
|------A.v
|------B.v
|------C.v
|------D.v

Let us suppose I have vpi system function in D.v and the system
function needs the signal from A.v. Is it possible for me to use
vpi_handle_by_name() from module D.v go up the heirarchy into module
A.v to get the signal. I should be calling this vpi from D.v only.

Thanks
S

 

[Homuncilus]

On 2ÔÂ3ČŐ, ÉĎÎç4Ęą43ˇÖ, sarma.nedun...@gmail.com wrote:

I have the following heirarchy in verilog

top.v-----
|------A.v
|------B.v
|------C.v
|------D.v

Let us suppose I have vpi system function in D.v and the system
function needs the signal from A.v. Is it possible for me to use
vpi_handle_by_name() from module D.v go up the heirarchy into module
A.v to get the signal. I should be calling this vpi from D.v only.

Thanks
S

I don't know what you meant.

 

On Feb 2, 3:43 pm, sarma.nedun...@gmail.com wrote:

Let us suppose I have vpi system function in D.v and the system
function needs the signal from A.v. Is it possible for me to use
vpi_handle_by_name() from module D.v go up the heirarchy into module
A.v to get the signal.

If the signal is an argument to the system function,
you should be able to use the normal Verilog syntax
to reference the signal from D (either an absolute or
relative hierarchical name).

If you are trying to get it directly without any argument,
you should be able to get it with vpi_handle_by_name()
using an absolute path from top, presumably top.A.name.

 

On Feb 3, 4:09 pm, s...@cadence.com wrote:

On Feb 2, 3:43 pm, sarma.nedun...@gmail.com wrote:



Thanks s..@cadence.com

I have a followup if A is vhdl module would the scenario differ. I get
to the instance of A but not to the signals of A.

Thanks
S

Let us suppose I have vpi system function in D.v and the system
function needs the signal from A.v. Is it possible for me to use
vpi_handle_by_name() from module D.v go up the heirarchy into module
A.v to get the signal.

If the signal is an argument to the system function,
you should be able to use the normal Verilog syntax
to reference the signal from D (either an absolute or
relative hierarchical name).

If you are trying to get it directly without any argument,
you should be able to get it with vpi_handle_by_name()
using an absolute path from top, presumably top.A.name.

 

sarma.nedunuri@gmail.com wrote:

I have a followup if A is vhdl module would the scenario differ. I get
to the instance of A but not to the signals of A.

Yes, I assume it would differ. The variables of A would be
VHDL objects, not Verilog objects, so I assume that VPI
is not designed to be able to access them. There is a
different C interface, VHPI, defined for accessing VHDL
design objects.

You might be able to use VHPI to access the contents
of your VHDL module, even though the path to it is
partly Verilog. I would expect a mixed-language tool
to support that.