VPI and nested modules

[Krzysiek Kowaliczek]

Hi,

How can I check is module is nested by VPI routines?
I have browsed the standard 1800-2009 completely,
but I cannot find any information about that.
Thanks.

Krzysiek

 

[Cary R.]

Krzysiek Kowaliczek wrote:

Hi,

How can I check is module is nested by VPI routines?
I have browsed the standard 1800-2009 completely,
but I cannot find any information about that.
Thanks.

I'm not exactly sure what you mean by nested. It could be is this module
instantiated inside another module or the special is this module
instantiated inside itself using a generate scheme. Though it doesn't
matter too much. If all you are looking for is is this an instantiation
then look for the vpiTopModule property equal to zero. You could also
check that the vpiFullName and vpiName are not the same value. If you
want to actually search up the hierarchy for more information then you
could use the vpiFullName and pop off the last name component to get the
parents name. If you have instantiations with an escaped identifier name
this is slightly more complicated, but this is usually not the case.
With the parents name you can use vpi_handle_by_name() to get a handle
to the parent. Get the information you need from the handle and iterate
as needed.

Cary

 

On Jun 18, 1:22 pm, "Cary R." <no-s...@host.spam> wrote:

Krzysiek Kowaliczek wrote:
Hi,

How can I check is module is nested by VPI routines?
I have browsed the standard 1800-2009 completely,
but I cannot find any information about that.
Thanks.

I'm not exactly sure what you mean by nested.

I assume he is talking about the SystemVerilog feature where a module
can be declared inside another module, instead of outside like normal
modules modules. No idea if there is any way for VPI to distinguish
this though.