Vivado HLS (C/C++/SystemC to ASIC/FPGA)

[Rick C. Hodgin]

Does anybody have experience with Vivado HLS?

https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html

This tool is very similar to the internal processes I have planned for
my Logician tool.

Best regards,
Rick C. Hodgin

 

[Rick C. Hodgin]

On Thursday, October 6, 2016 at 6:22:32 AM UTC-4, Rick C. Hodgin wrote:

Does anybody have experience with Vivado HLS?

https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html

This tool is very similar to the internal processes I have planned for
my Logician tool.

They have a free 30-day evaluation. I may find out what hardware I'll
need and schedule a time where I can devote a month to learning more
about this tool:

https://www.xilinx.com/products/design-tools/vivado.html#buy

My Logician tool plans to be like Blender's node editor, with things
connected graphically like that, with source code and logic contained
within each node. I have planned on making the source code a subset
of my CAlive language currently under development, with limited support
for local and global variables.

I can see the possibility from watching this video:

C to FPGA Compilation and Domain-Specific Computing
https://www.youtube.com/watch?v=TNF8EhKDM1c

....that there exists an interesting potential of analyzing the data
usage, and determining what type of CPU would be be applied to this
application, and in that way creating a literal custom CPU with an
ISA designed for the needs of the tasks, which would allow for a quick
and completely programmable CPU to be custom fabricated per the needs
of each app, ultimately creating heterogeneous cores which run in
massive parallel on a target FPGA for a given application.

Logician would handle the wiring and source code, and the compiler
would handle the details of taking that source design and generating
a workable and viable stand-alone CPU with periphery ties.

This will be my goal with Logician.

Best regards,
Rick C. Hodign