N
Nitin Jain
Guest
Hi all,
Does anybody know what are basic techniques to achieve a throughput
of 4 bits per clock in FPGA for a viterbi decoder. Basically, what I
want is the following:
(1.) If I clock Viterbi decoder at clock frequency of 50 MHz to
implement in FPGA/ASIC, what basic algorithm should I choose to
achieve 200 Mbps throughput that means computing 4 decoding bits per
clock. Any thoughts on this will be appreciated.
Thanks and Regards
Nitin
Does anybody know what are basic techniques to achieve a throughput
of 4 bits per clock in FPGA for a viterbi decoder. Basically, what I
want is the following:
(1.) If I clock Viterbi decoder at clock frequency of 50 MHz to
implement in FPGA/ASIC, what basic algorithm should I choose to
achieve 200 Mbps throughput that means computing 4 decoding bits per
clock. Any thoughts on this will be appreciated.
Thanks and Regards
Nitin