H
Heliboy
Guest
Folks,
I am trying to put the large Path Memory for Trace Back of Viterbi
Decoder in Block RAM of Xilinx Viterx FPGA. Say we have a 64 states,
trellis depth of 100 Trace Back and one decoded bit is output every
clock cycle. The problem is that how to store this path memory in
Block RAM? As far as I know that the Block RAM can only be
read/written in one address every clock cycle, prohit it from tracing
back through the long depth of trellis in one clock cycle. One
solution is to use many Block RAMs but it will need lots RAMs (Many
implementations said they only need couple of Block RAMs). Am I
missing something here? Tanks.
I am trying to put the large Path Memory for Trace Back of Viterbi
Decoder in Block RAM of Xilinx Viterx FPGA. Say we have a 64 states,
trellis depth of 100 Trace Back and one decoded bit is output every
clock cycle. The problem is that how to store this path memory in
Block RAM? As far as I know that the Block RAM can only be
read/written in one address every clock cycle, prohit it from tracing
back through the long depth of trellis in one clock cycle. One
solution is to use many Block RAMs but it will need lots RAMs (Many
implementations said they only need couple of Block RAMs). Am I
missing something here? Tanks.