vital question

J

JohnSmith

Guest
Hi,

I'm studying simulating a simple AND gate (in Xilinx). Xilinx uses
X_AND2 for this. I found that "variable O_GlitchData" is uninitialized
when calling VitalPathDelay01 routine from "timing_b" package at this
line "GlitchData.SchedTime <= NOW". Is this really uninitialized or I
missed sg.? I know Xilinx maybe uses an accelerated version of this
component, I just want to know that is correct or not.


(1)
architecture X_AND2_V of X_AND2 is

attribute VITAL_LEVEL1 of
X_AND2_V : architecture is true;

signal I0_ipd : std_ulogic := 'X';
signal I1_ipd : std_ulogic := 'X';
begin
WireDelay : block
begin
VitalWireDelay (I0_ipd, I0, tipd_I0);
VitalWireDelay (I1_ipd, I1, tipd_I1);
end block;

VITALBehavior : process (I0_ipd, I1_ipd)
variable O_zd : std_ulogic;
variable O_GlitchData : VitalGlitchDataType;
begin
O_zd := I0_ipd and I1_ipd;
VitalPathDelay01 (
OutSignal => O,
GlitchData => O_GlitchData,
OutSignalName => "O",
OutTemp => O_zd,
Paths => (0 => (I0_ipd'last_event, tpd_I0_O, true),
1 => (I1_ipd'last_event, tpd_I1_O, true)),
Mode => VitalTransport,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
end process;
end X_AND2_V;

(2) PROCEDURE VitalPathDelay01 (

BEGIN
-- Check if the new value to be scheduled is different than
the
-- previously scheduled value
IF (GlitchData.SchedTime <= NOW) AND
(GlitchData.SchedValue = OutTemp)
THEN RETURN;
END IF;


John
 
On Aug 24, 2:09 pm, JohnSmith <csnew...@gmail.com> wrote:
Hi,

I'm studying simulating a simple AND gate (in Xilinx). Xilinx uses
X_AND2 for this. I found that "variable O_GlitchData" is uninitialized
when calling VitalPathDelay01 routine from "timing_b" package at this
line "GlitchData.SchedTime <= NOW". Is this really uninitialized or I
missed sg.? I know Xilinx maybe uses an accelerated version of this
component, I just want to know that is correct or not.

(1)
architecture X_AND2_V of X_AND2 is

attribute VITAL_LEVEL1 of
X_AND2_V : architecture is true;

signal I0_ipd : std_ulogic := 'X';
signal I1_ipd : std_ulogic := 'X';
begin
WireDelay : block
begin
VitalWireDelay (I0_ipd, I0, tipd_I0);
VitalWireDelay (I1_ipd, I1, tipd_I1);
end block;

VITALBehavior : process (I0_ipd, I1_ipd)
variable O_zd : std_ulogic;
variable O_GlitchData : VitalGlitchDataType;
begin
O_zd := I0_ipd and I1_ipd;
VitalPathDelay01 (
OutSignal => O,
GlitchData => O_GlitchData,
OutSignalName => "O",
OutTemp => O_zd,
Paths => (0 => (I0_ipd'last_event, tpd_I0_O, true),
1 => (I1_ipd'last_event, tpd_I1_O, true)),
Mode => VitalTransport,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
end process;
end X_AND2_V;

(2) PROCEDURE VitalPathDelay01 (

BEGIN
-- Check if the new value to be scheduled is different than
the
-- previously scheduled value
IF (GlitchData.SchedTime <= NOW) AND
(GlitchData.SchedValue = OutTemp)
THEN RETURN;
END IF;

John
Click to expand...
Everything in VHDL is initialized. If not explicitly so in the code,
then the rightmost defined value is the initial value. This applies to
scalar elements only; compound elements are initialized with the
initial values of their constituent scalars.

Andy
 
On Aug 25, 10:57 pm, Andy <jonesa...@comcast.net> wrote:
On Aug 24, 2:09 pm, JohnSmith <csnew...@gmail.com> wrote:



Hi,

I'm studying simulating a simple AND gate (in Xilinx). Xilinx uses
X_AND2 for this. I found that "variable O_GlitchData" is uninitialized
when calling VitalPathDelay01 routine from "timing_b" package at this
line "GlitchData.SchedTime <= NOW". Is this really uninitialized or I
missed sg.? I know Xilinx maybe uses an accelerated version of this
component, I just want to know that is correct or not.

(1)
architecture X_AND2_V of X_AND2 is

attribute VITAL_LEVEL1 of
X_AND2_V : architecture is true;

signal I0_ipd : std_ulogic := 'X';
signal I1_ipd : std_ulogic := 'X';
begin
WireDelay : block
begin
VitalWireDelay (I0_ipd, I0, tipd_I0);
VitalWireDelay (I1_ipd, I1, tipd_I1);
end block;

VITALBehavior : process (I0_ipd, I1_ipd)
variable O_zd : std_ulogic;
variable O_GlitchData : VitalGlitchDataType;
begin
O_zd := I0_ipd and I1_ipd;
VitalPathDelay01 (
OutSignal => O,
GlitchData => O_GlitchData,
OutSignalName => "O",
OutTemp => O_zd,
Paths => (0 => (I0_ipd'last_event, tpd_I0_O, true),
1 => (I1_ipd'last_event, tpd_I1_O, true)),
Mode => VitalTransport,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
end process;
end X_AND2_V;

(2) PROCEDURE VitalPathDelay01 (

BEGIN
-- Check if the new value to be scheduled is different than
the
-- previously scheduled value
IF (GlitchData.SchedTime <= NOW) AND
(GlitchData.SchedValue = OutTemp)
THEN RETURN;
END IF;

John

Everything in VHDL is initialized. If not explicitly so in the code,
then the rightmost defined value is the initial value. This applies to
scalar elements only; compound elements are initialized with the
initial values of their constituent scalars.

Andy
Click to expand...
What is the default value of a "time" type variable?
 
On Aug 25, 9:13 pm, JohnSmith <csnew...@gmail.com> wrote:
On Aug 25, 10:57 pm, Andy <jonesa...@comcast.net> wrote:



On Aug 24, 2:09 pm, JohnSmith <csnew...@gmail.com> wrote:

Hi,

I'm studying simulating a simple AND gate (in Xilinx). Xilinx uses
X_AND2 for this. I found that "variable O_GlitchData" is uninitialized
when calling VitalPathDelay01 routine from "timing_b" package at this
line "GlitchData.SchedTime <= NOW". Is this really uninitialized or I
missed sg.? I know Xilinx maybe uses an accelerated version of this
component, I just want to know that is correct or not.

(1)
architecture X_AND2_V of X_AND2 is

attribute VITAL_LEVEL1 of
X_AND2_V : architecture is true;

signal I0_ipd : std_ulogic := 'X';
signal I1_ipd : std_ulogic := 'X';
begin
WireDelay : block
begin
VitalWireDelay (I0_ipd, I0, tipd_I0);
VitalWireDelay (I1_ipd, I1, tipd_I1);
end block;

VITALBehavior : process (I0_ipd, I1_ipd)
variable O_zd : std_ulogic;
variable O_GlitchData : VitalGlitchDataType;
begin
O_zd := I0_ipd and I1_ipd;
VitalPathDelay01 (
OutSignal => O,
GlitchData => O_GlitchData,
OutSignalName => "O",
OutTemp => O_zd,
Paths => (0 => (I0_ipd'last_event, tpd_I0_O, true),
1 => (I1_ipd'last_event, tpd_I1_O, true)),
Mode => VitalTransport,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
end process;
end X_AND2_V;

(2) PROCEDURE VitalPathDelay01 (

BEGIN
-- Check if the new value to be scheduled is different than
the
-- previously scheduled value
IF (GlitchData.SchedTime <= NOW) AND
(GlitchData.SchedValue = OutTemp)
THEN RETURN;
END IF;

John

Everything in VHDL is initialized. If not explicitly so in the code,
then the rightmost defined value is the initial value. This applies to
scalar elements only; compound elements are initialized with the
initial values of their constituent scalars.
Click to expand...
Actually, the initial default value is T'LEFT, not the rightmost.

Andy

What is the default value of a "time" type variable?
Click to expand...
From the LRM-2000 "The range of TIME is implementation dependent, but
it is guaranteed to include the range –2147483647 to +2147483647."

Strictly, speaking, VHDL LRM (2000 edition) therefore doesn't appear
to define the initial value for time,(yeah, this surprised me, too !!
Maybe 2002 or '06 changed it). I looked in one copy of 'standard.vhd'
and it used the range "-2147483647 to 2147483647" which would give you
roughly -2e9 fs (or a paltry -2e3 ns). But then a 64-bit
implementation *might* give you a different default. Recall that a
regular physical type range is always in terms of the *primary* unit,
which is femtoseconds. This inability to express time beyond 2 ns
doesn't make a lot of sense unless it's being overridden by the
resolution limit of a particular implementation - time is a funny
thing in VHDL.

I guess defining the initial value of time is one of those larger
metaphysical questions - perhaps the ambiguity in VHDL mimics the
human, anthropomorphic uncertainty :)

- Kenn
 
On Aug 29, 4:56 pm, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org>
wrote:
What 2000 edition of the VHDL LRM?
Click to expand...
See for example

http://www.doulos.com/knowhow/vhdl_designers_guide/a_brief_history_of_vhdl/

The 2002 edition also has time as an implementation defined range.

The weird thing is that all physical types are discrete and are
defined in terms of their primary unit, meaning that when a physical
type is defined as -2 billion to + 2 billion with a primary unit of
ps, that really only gives it a range of plus-minus 2 thousand ns. I
can't find the part in the LRM that explains why it's legal to talk
about 2 billion ns given the above definition. Clearly, that was the
*intent* of the whole business with the resolution limit, but the only
thing I can find says that the resolution limit lets you turn small
values into *zero*. But nothing that says that when you fiddle the
resolution limit, there's a corresponding magical increase in the
underlying anonymous discrete scalar type. Nit-picking, I'm sure, but
I like my reference documents to be clear and internally consistent.

- Kenn
 
On Aug 30, 9:34 am, kennheinr...@sympatico.ca wrote:
meaning that when a physical
type is defined as -2 billion to + 2 billion with a primary unit of
ps, that really only gives it a range of plus-minus 2 thousand ns.  I
Click to expand...
Oops, meant to write primary unit fs (femtoseconds), not ps.

- Kenn
 
JohnSmith wrote:

Your previous website (http://home.comcast.net/~mike_treseler/) is
available now? It seems it is down..
Click to expand...
That site has moved to

http://mysite.verizon.net/miketreseler/
 
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