vital question

Guest
Hello
I am trying to model assign statement in verilog using the
conditional operator using VHDL and using if statement. I get a VITAL
error

** Error: PUSB2.vhd(357): If Statement in VITAL_LEVEL1 process cannot
have else or elsif clause.
(1076.4 section 6.4.3)
** Error: PUSB2.vhd(357): If Statement condition in VITAL_LEVEL1
process must be the TimingChecksOn control generic.
(1076.4 section 6.4.3)
** Error: PUSB2.vhd(357): Timing check section must precede
functionality section.
(1076.4 section 6.4.3.2)
** Error: PUSB2.vhd(358): If Statement in VITAL_LEVEL1 process can
contain only VITAL timing check calls.
(1076.4 section 6.4.3)
** Error: PUSB2.vhd(363): If Statement in VITAL_LEVEL1 process cannot
have else or elsif clause.
(1076.4 section 6.4.3)
** Error: PUSB2.vhd(363): If Statement condition in VITAL_LEVEL1
process must be the TimingChecksOn control generic.
(1076.4 section 6.4.3)

How can I not use if statement in VITAL? Or is there an alternmate way
without using if statement

assign OE11 = ((SPEED0 & ~SPEED1)|(SPEED1 & ~SPEED0)) ? OE : 1'b0;

This is statement in Verilog I am trying to model in VHDL using if
statement

Thanks
krithiga
 
On 20 Jun 2006 09:45:46 -0700, krithiga81@yahoo.com wrote:

I am trying to model assign statement in verilog using the
conditional operator using VHDL and using if statement. I get a VITAL
error
Click to expand...
Why are you trying to use the VITAL library for this? It's far
simpler just to write some regular VHDL code.

assign OE11 = ((SPEED0 & ~SPEED1)|(SPEED1 & ~SPEED0)) ? OE : 1'b0;
Click to expand...
You cannot *exactly* mimic the Verilog continuous assign in VHDL,
because Verilog continuous assignment updates its target without a
delta delay; but if you are only concerned to model the correct
functional behaviour, or you are writing code for synthesis, then
it's rather easy to make the translation.

(1) Re-write the Verilog assign as an always block:

always @(SPEED0 or SPEED1 or OE) begin
OE11 = ((SPEED0 & ~SPEED1)|(SPEED1 & ~SPEED0)) ? OE : 1'b0;
end

(2) Replace the conditional operator with an IF statement, because
VHDL has no conditional operator:

always @(SPEED0 or SPEED1 or OE) begin
if ((SPEED0 & ~SPEED1)|(SPEED1 & ~SPEED0))
OE11 = OE;
else
OE11 = 1'b0;
end

(3) Trivially translate into VHDL (with appropriate
signal declarations in the top of the architecture):

process (SPEED0, SPEED1, OE)
begin
if ((SPEED0 and not SPEED1) or (SPEED1 and not SPEED0)) = '1' then
OE11 <= OE;
else
OE11 <= '0';
end if;
end process;

At some point in this procedure you may perhaps note that
your IF condition is more easily written as (SPEED0 xor SPEED1).

Some people will tell you to use a VHDL conditional concurrent
signal assignment instead:

OE11 <= OE when (SPEED0 xor SPEED1) = '1' else '0';

but I find that very clumsy; I prefer to write the process
in full. The effect is identical; it's a style choice.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Hello
Thanks. The reason I use VITAL is because we are supposed to me
modeling using VITAL standards. If I use IF statement I get the error I
mentioned in the posting. If I use
OE11 <==

Then I define OE11 as a signal and when I define OE11 as signal it
complains that Signal
Signal declaration 'oe11 not allowed in this region'

Please let me know

Thanks
kc
Jonathan Bromley wrote:
On 20 Jun 2006 09:45:46 -0700, krithiga81@yahoo.com wrote:

I am trying to model assign statement in verilog using the
conditional operator using VHDL and using if statement. I get a VITAL
error

Why are you trying to use the VITAL library for this? It's far
simpler just to write some regular VHDL code.

assign OE11 = ((SPEED0 & ~SPEED1)|(SPEED1 & ~SPEED0)) ? OE : 1'b0;

You cannot *exactly* mimic the Verilog continuous assign in VHDL,
because Verilog continuous assignment updates its target without a
delta delay; but if you are only concerned to model the correct
functional behaviour, or you are writing code for synthesis, then
it's rather easy to make the translation.

(1) Re-write the Verilog assign as an always block:

always @(SPEED0 or SPEED1 or OE) begin
OE11 = ((SPEED0 & ~SPEED1)|(SPEED1 & ~SPEED0)) ? OE : 1'b0;
end

(2) Replace the conditional operator with an IF statement, because
VHDL has no conditional operator:

always @(SPEED0 or SPEED1 or OE) begin
if ((SPEED0 & ~SPEED1)|(SPEED1 & ~SPEED0))
OE11 = OE;
else
OE11 = 1'b0;
end

(3) Trivially translate into VHDL (with appropriate
signal declarations in the top of the architecture):

process (SPEED0, SPEED1, OE)
begin
if ((SPEED0 and not SPEED1) or (SPEED1 and not SPEED0)) = '1' then
OE11 <= OE;
else
OE11 <= '0';
end if;
end process;

At some point in this procedure you may perhaps note that
your IF condition is more easily written as (SPEED0 xor SPEED1).

Some people will tell you to use a VHDL conditional concurrent
signal assignment instead:

OE11 <= OE when (SPEED0 xor SPEED1) = '1' else '0';

but I find that very clumsy; I prefer to write the process
in full. The effect is identical; it's a style choice.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
 
Then I define OE11 as a signal and when I define OE11 as signal it
complains that Signal
Signal declaration 'oe11 not allowed in this region'
Click to expand...
Signals should be declared after the architecture and before the begin.
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top