vital modeling on Path Delays

Guest
Hello
I am trying to model an equivalent from Verilog to Vital and it has
if ((SPEED1 == 1'b0)&&(SPEED0 == 1'b1))
(TXDP *> DP) = (1.000, 1.000);

So in Vital I am
VitalPathDelay01Z(
OutSignal => DP,
OutSignalName => "DP",
OutTemp => DP_zd,
Paths => (
0 => ( TXDP_ipd'LAST_EVENT,

VitalExtendToFillDelay(tpd_TXDP_DP_SPEED1_EQ_0_AN_tpd_TXDP_DP
_SPEED0_EQ_1),
(To_X01(SPEED1_ipd) /= '1') ),

to the X01 function I can only use one signal. How do I feed the 2
signals to X01 the 2 signals are SPEED1_ipd /= 1 and SPEED0_ipd /= 0

Thanks
kc
 
Hello
Can anyone please respond to my question?

Thanks
krithiga

krithiga81@yahoo.com wrote:
Hello
I am trying to model an equivalent from Verilog to Vital and it has
if ((SPEED1 == 1'b0)&&(SPEED0 == 1'b1))
(TXDP *> DP) = (1.000, 1.000);

So in Vital I am
VitalPathDelay01Z(
OutSignal => DP,
OutSignalName => "DP",
OutTemp => DP_zd,
Paths => (
0 => ( TXDP_ipd'LAST_EVENT,

VitalExtendToFillDelay(tpd_TXDP_DP_SPEED1_EQ_0_AN_tpd_TXDP_DP
_SPEED0_EQ_1),
(To_X01(SPEED1_ipd) /= '1') ),

to the X01 function I can only use one signal. How do I feed the 2
signals to X01 the 2 signals are SPEED1_ipd /= 1 and SPEED0_ipd /= 0

Thanks
kc
Click to expand...
 
krithiga81@yahoo.com wrote:
Hello
Can anyone please respond to my question?
http://www.google.com/search?q=vhdl+vital+modeling+Path+Delays
Click to expand...
 
Hi
I did do a google search earlier but to my particular case I was not
able to find a solution for X01 functionality

Thanks
krithiga
Mike Treseler wrote:
krithiga81@yahoo.com wrote:
Hello
Can anyone please respond to my question?
http://www.google.com/search?q=vhdl+vital+modeling+Path+Delays
Click to expand...
 
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