visualise"type" in wave window

[Clunixchit]

Hello there,
in my .vhdl file, i have declared a type, such as:
type state is (wait0, wait1, wait2, wait3);
signal state : actual_state;

how can I visualise it in the wave window of modelsim ?

regards
Chitlesh

 

[Mike Treseler]

Clunixchit wrote:

in my .vhdl file, i have declared a type, such as:
type state is (wait0, wait1, wait2, wait3);
signal state : actual_state;

how can I visualise it in the wave window of modelsim ?

For a vhdl testbench, it just works if I add wave.

vsim my_tb
add wave *
run

for example see the signal op_now here:
http://home.comcast.net/~mike_treseler/oe_demo.pdf


-- Mike Treseler

 

[Clunixchit]

On May 27, 12:37 pm, Mike Treseler wrote:

For a vhdl testbench, it just works if I add wave.

vsim my_tb
add wave *
run

Thanks but it wasn't what i was looking for.
Actually my type "state" wasn't written in the testbench.

I've found out how to do so.

Solution:
view -> structure
(select the architecture)
view signals
(select state)
right click, add to waves (selected)

regards,
Chitlesh

 

[Mike Treseler]

Clunixchit wrote:

Solution:
view -> structure
(select the architecture)
view signals
(select state)
right click, add to waves (selected)

Yes, or

add wave -r /*

at the prompt.

-- Mike Treseler