A
Achintya
Guest
Hello,
Can anybody say if we can do a flattening of the schematic netlist to
an arbitratry level?
....Because the netlist flattening tool in cadence design tools flattens
the netlist to lowest level that is till the library defined elements
such as the pmos and nmos...but what we want is to flatten till a user
defined symbol.
-vs_p.
Can anybody say if we can do a flattening of the schematic netlist to
an arbitratry level?
....Because the netlist flattening tool in cadence design tools flattens
the netlist to lowest level that is till the library defined elements
such as the pmos and nmos...but what we want is to flatten till a user
defined symbol.
-vs_p.