Virtuoso: missing solder...not missing

K

Konx

Guest
Hi.

I try to ask here, because I'm going crazy.

I have this Pixel schematic. Until last friday the simulations of the
schematic view were working perfectly. Friday, ADE, for some reasons,
decide to doesn't work anymore: when I run the simulation I have this
error: Failed to partition the design.

ERROR (ADE-3010): Cannot create and partition the design.
ERROR (ADE-3009): There are errors in the designs. Fix these before
netlisting.

First: I made no change in my design, so I can't really understand why
Thursday the simulations were working and Friday not...but, let's say
that something strange is going on and a ghost has modify my
schematic.

Now, if I check the schematic I have 9 warning in one block called
Controller: in the Virtuoso log window I can see that there are
warnings like this:

Warning: Solder dot on cross over at ( 26.2500, 13.1250 ).

The problem is that if I open the schematic and try to see where are
these warning...well, the solder are there!

(specification: Controller's schematic has been produced from a
Verilog netlist, but neither the verilog nor the schematic have been
modified).

Do you have any thoughts?

Thanks in advance

Francesco.

(personal comment: I started working through IC design flow 2 months
ago...I hope things will be a little bit easier in the future,
otherwise I can predict a suicide here :p)
 
Hi Francesco,

There must be a silly mistake somewhere ...

1. Warning: Solder dot on cross over at ( 26.2500, 13.1250 ).
You can get rid of this warning by doing the following from your
Virtuoso Schematic window:
Go to menu Check >=-> Rules Setup. In the Setup Schematic Rules Check
form, click the 'Physical' tab and then switch the 'Solder On
CrossOver' to 'ignored' instead of 'warning'.
This would disable this warning. If you want to make this option
available all the time, then I'd advise you creating a file called
'.cdsenv' in your UNIX home directory and add the following:
schematic srcSolderOnCrossover cyclic "ignored"

I'm doubting the above warning was responsible of your ADE crash. ADE
shouldn't crash on such a warning.
To solve your ADE problem, I'd proceed as following:
1. Check and save you design. You may check the entire hierarchy using
meny Check -> Hierarchy. Look at you CIW for any errors that might
occur.
2. Go to ADE -> Simulation -> Netlist -> Recreate
3. Run the simulation.

If the above does not solve the problem, then
1. Shut down you Cadence session altogether
2. Delete your simulation directory.
3. Start a new UNIX terminal.
4. Browse to your project directory and source whatever file that
allows you loading your Tools, PDKs ... etc.
5. Launch Cadence.
6. Open your design again -> Open ADE and move forward with the next
Steps.

If the above does not work then .... you may tells us more about your
stuff, but don't commit a suicide ...

Cheers,
Riad.
 
On Aug 31, 1:46 pm, Riad KACED <riad.ka...@gmail.com> wrote:

[cut]

If the above does not work then .... you may tells us more about your
stuff, but don't commit a suicide ...
Click to expand...
Hi Riad,

as always thanks for help :)

I tried everything you said, but still the simulation is not working.
In the CIW window I have a bunch of warning like this one:

*USRWARN: Terminal in, of instance I1 (referring to placed master
NikhefWork.inv_osc_slow.symbol), residing in cellview
(NikhefWork.inv_osc_slow_4.schematic, using configViewString schematic
spectre verilog verilog2 functional verilogams cmos_sch cmos.sch
extracted veriloga primitive) cannot be matched with any port
in the instance's simulation master Module inv_osc_slow, lib
NikhefWork, view schematic, configViewString schematic spectre verilog
verilog2 functional verilogams cmos_sch cmos.sch extracted veriloga
primitive.
Please run Schematic Hierarchical Checker.

Now, I tried to dig in deep in this error but honestly it is a bit
hard to understand. I mean: the component exists in the scehmatic
(obviously) but all the connections are ok, and I can't understand why
ADE is complaining about it.

Others (maybe) useful informations: I tried to run the simulations
from another PC (the one where my supervisor is working(, and they
run! So, it seems that the problem is local to my settings or to my
environment...what could I check?

The only thing that comes to my mind is that something was going wrong
with the new PDK that has been installed last week. I changed my
settings as my supervisor told me, but...who knows, maybe there is
still something to do (but it would be strange because all is going on
ok in my supervisor's PC, as I said).

Well, I can imagine that it is really difficult to debug :)

Thanks again

Francesco.
 
On Aug 31, 3:44 pm, Konx <cesco...@gmail.com> wrote:

[cut]

An additional information: all the warnings I have during the
netlisting performed by ADE are referred to the same Library
NikhefWork...a problem in the permission of the library, maybe?

Francesco.
 
Hi Francesco,

A bit hard to sort out this remotely ...
You said it worked fine from your supervisor's PC, was that using your
UNIX account or your supervisors ?
How do you share the data between you and your supervisor ? Are you
using any data management system, like designSync for example ?
What if you recreate the config view altogether ?

Since your supervisor is able to run the simulation properly, then I'd
advise comparing your environment to his. Just check you are pointing
to the same PDKs, libraries ... etc.
I'm afraid I have not got all the tools to remotely debug your design
remotely. Best is to ask your supervisor for help. I'm sure your
problem is rather tied to the environment/PDk rather than the tool
itself.

You might want to share your CDS.log.
Andrew may have better ideas to help you I suppose. Today is a public
holiday in the UK though ...

Cheers,
Riad.
 
On Sep 1, 11:40 am, Konx <cesco...@gmail.com> wrote:

[cut]

Ok, just to inform you: we finally solved the problem. The problem was
in a wrong library path, in the NikhefWork: basically, it was pointing
to an old version and because of the last week change in the PDK maybe
something went wrong (actually, I'm not sure of the explanation, but
now the simulations are working again and I'm more happy :p)

Thanks for help!

Francesco.
 
On Aug 31, 11:37 am, Konx <cesco...@gmail.com> wrote:
Hi.

I try to ask here, because I'm going crazy.

I have this Pixel schematic. Until last friday the simulations of the
schematic view were working perfectly. Friday, ADE, for some reasons,
decide to doesn't work anymore: when I run the simulation I have this
error: Failed to partition the design.

ERROR (ADE-3010): Cannot create and partition the design.
ERROR (ADE-3009): There are errors in the designs. Fix these before
netlisting.

First: I made no change in my design, so I can't really understand why
Thursday the simulations were working and Friday not...but, let's say
that something strange is going on and a ghost has modify my
schematic.

Now, if I check the schematic I have 9 warning in one block called
Controller: in the Virtuoso log window I can see that there are
warnings like this:

Warning: Solder dot on cross over at ( 26.2500, 13.1250 ).

The problem is that if I open the schematic and try to see where are
these warning...well, the solder are there!

(specification: Controller's schematic has been produced from a
Verilog netlist, but neither the verilog nor the schematic have been
modified).

Do you have any thoughts?

Thanks in advance

Francesco.

(personal comment: I started working through IC design flow 2 months
ago...I hope things will be a little bit easier in the future,
otherwise I can predict a suicide here :p)
Click to expand...
Hi

There must be a silly mistake somewhere ...

1. Warning: Solder dot on cross over at ( ... ).
You can get rid of this warning by doing the following from your
Virtuoso Schematic window:
Go to menu Check >=-> Rules Setup. In the Setup Schematic Rules Check
form, click the 'Physical' tab and then switch the 'Solder On
CrossOver' to 'ignored' instead of 'warning'.
This would disable this warning. If you want to make this option
available all the time, then I'd advise you creating a file called
'.cdsenv' in your UNIX home directory and add the following:
schematic srcSolderOnCrossover cyclic "ignored"

I'm doubting the above warning was responsible of your ADE crash. ADE
shouldn't crash on such a warning.
To solve your ADE problem, I'd proceed as following:
1. Check and save you design. You may check the entire hierarchy using
meny Check -> Hierarchy. Look at you CIW for any errors that might
occur.
2. Go to ADE -> Simulation -> Netlist -> Recreate
3. Run the simulation.

If the above does not solve the problem, then
1. Shut down you Cadence session altogether
2. Delete your simulation directory.
3. Start a new UNIX terminal.
4. Browse to your project directory and source whatever file that
allows you loading your Tools, PDKs ... etc.
5. Launch Cadence.
6. Open your design again -> Open ADE and move forward with the next
Steps.

If the above does not work then .... you may tells us more about your
stuff, but don't commit a suicide ...

Cheers,
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top