J
John Gianni
Guest
Good news.
SUMMARY:
Inherited Connections Tutorial (part 1), including layout & physical
verification & creation of LEF abstracts & DFII abstracts ...
DETAILS:
The good news is that part 1 of the new "Virtuoso Inherited
Connections Flow Guide" (containing a small sample 180nm design &
design kit with inherited connections) was just released today on
Sourcelink for Customer use!
You can pick up the design, design kit, & documented flow at:
http://sourcelink.cadence.com/docs/files/Tutorials/inheritedconnectiontutorial.html
Here is the wording at that URL if you're unfamiliar with INHERITED
CONNECTIONS:
Inherited connections are an extension to the connectivity model that
allow you to create signals hierarchically and to override their names
for selected branches of a design hierarchy. This flexibility allows
you to design:
* Parameterized power and ground signals
* Overridable substrate connections
* Multiple power supplies for a design
Download the tutorial database and the "VirtuosoŽ Inherited
Connections Flow Guide" manual to learn more about using inherited
connections with Cadence tools. The manual contains illustrations and
step-by-step instructions that show how inherited connections let you
selectively override signals in designs created with the VirtuosoŽ
Schematic Editor, and how those connections are available to other
Cadence tools across the design flow.
Download the Tutorial on UNIX/Linux (File size: 15MB)
Coming Soon
The Virtuoso Inherited Connections Flow Guide manual is a
work-in-progress.
We will be extending its depth and breath and plan to cover more of
the complete design process in the future. Please check this location
on SourceLink again for the next version, to learn about:
* The difference between implicit terminals and explicit pins
* How and when to use implicit terminals versus explicit pins
* Inherited connections in AMS Designer using supply sensitivity
* Interaction with the verification environment (ASSURA LVS) or
with parasitic resimulation
John Gianni
Director, Flow Engineering
Nothing I post to the USENET is company ordered nor sanctioned.
SUMMARY:
Inherited Connections Tutorial (part 1), including layout & physical
verification & creation of LEF abstracts & DFII abstracts ...
DETAILS:
The good news is that part 1 of the new "Virtuoso Inherited
Connections Flow Guide" (containing a small sample 180nm design &
design kit with inherited connections) was just released today on
Sourcelink for Customer use!
You can pick up the design, design kit, & documented flow at:
http://sourcelink.cadence.com/docs/files/Tutorials/inheritedconnectiontutorial.html
Here is the wording at that URL if you're unfamiliar with INHERITED
CONNECTIONS:
Inherited connections are an extension to the connectivity model that
allow you to create signals hierarchically and to override their names
for selected branches of a design hierarchy. This flexibility allows
you to design:
* Parameterized power and ground signals
* Overridable substrate connections
* Multiple power supplies for a design
Download the tutorial database and the "VirtuosoŽ Inherited
Connections Flow Guide" manual to learn more about using inherited
connections with Cadence tools. The manual contains illustrations and
step-by-step instructions that show how inherited connections let you
selectively override signals in designs created with the VirtuosoŽ
Schematic Editor, and how those connections are available to other
Cadence tools across the design flow.
Download the Tutorial on UNIX/Linux (File size: 15MB)
Coming Soon
The Virtuoso Inherited Connections Flow Guide manual is a
work-in-progress.
We will be extending its depth and breath and plan to cover more of
the complete design process in the future. Please check this location
on SourceLink again for the next version, to learn about:
* The difference between implicit terminals and explicit pins
* How and when to use implicit terminals versus explicit pins
* Inherited connections in AMS Designer using supply sensitivity
* Interaction with the verification environment (ASSURA LVS) or
with parasitic resimulation
John Gianni
Director, Flow Engineering
Nothing I post to the USENET is company ordered nor sanctioned.