virtual interface

[ramnarayan]

Hi,
can anyone suggest me when we should use virtual interface and
whats difference
between task and function in system verilog.

hoping positive response


Ramnarayan

 

[Ajeetha]

Hi Ram,
Virtual interface provides you the flexibility to dynamically
connect to different signals/interface during simulation inside a SVTB
framework. I would recommend you looking at SV LRM, Chris Spear's
Systemverilog for Verification book and our recent book on "Pragmatic
approach to VMM adoption" (See: http://www.systemverilog.us/) to learn
more on how to properly use it for maximum reuse/portability.

On task vs. function - it is similar to what verilog has - tasks can
consume time, function can't. Besides, SV has relaxed some rules for
functions such as there can be void functions, return values can be
omitted etc.

HTH
Ajeetha, CVC
www.noveldv.com
Contemporary Verification Consultants Pvt Ltd. http://www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
http://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar

ramnarayan wrote:

Hi,
can anyone suggest me when we should use virtual interface and
whats difference
between task and function in system verilog.

hoping positive response


Ramnarayan