VIRTEXII IO problem

[Yttrium]

Hey, i have this problem when i want to do the following thing:

I have this serial input (let's call it a) and i want to see the serial
input a through an IO provided on my evaluation board (let's call that pin
atest) and i did it like this

entity testmodule is
port(
a, clk: in std_logic;
b, atest: out std_logic
);
end testmodule;

architecture Behavioral of testmodule is

begin

-- the rest of the program to get a =>b

--with this process i want to feed the input a to and debug output atest
which it clocked on the clk (which is a lot
--faster than the serial clock so there should be no problem there
process(clk)
begin
if (clk'event and clk='1') then
atest<=a;
end if;
end process;

--OR can i just write the following;
atest<=a;

end Behavioral;

so i used a process to bring a => atest as a first method and then atest<=a
as a second method.
How come neither of these methods work??? did i miss something?

thanx in advance;

Yttrium

 

[Paulo Dutra]

I'm guessing this produces a multiple drivers error in synthesis.
Is this what you meant by "How come neither of these methods work???"


Yttrium wrote:

Hey, i have this problem when i want to do the following thing:

I have this serial input (let's call it a) and i want to see the serial
input a through an IO provided on my evaluation board (let's call that pin
atest) and i did it like this

entity testmodule is
port(
a, clk: in std_logic;
b, atest: out std_logic
);
end testmodule;

architecture Behavioral of testmodule is

begin

-- the rest of the program to get a =>b

--with this process i want to feed the input a to and debug output atest
which it clocked on the clk (which is a lot
--faster than the serial clock so there should be no problem there
process(clk)
begin
if (clk'event and clk='1') then
atest<=a;
end if;
end process;

--OR can i just write the following;
atest<=a;

end Behavioral;

so i used a process to bring a => atest as a first method and then atest<=a
as a second method.
How come neither of these methods work??? did i miss something?

thanx in advance;

Yttrium

--
/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
\ \ ` Xilinx hotline@xilinx.com
/ / 2100 Logic Drive http://www.xilinx.com
\_\/.\ San Jose, California 95124-3450 USA

 

[Yttrium]

well,when i let synthesis en implementation do their thing in ISE 5.2i they
don't give any problem ... (no errors and no warnings concerning this) ...
and i tried the one without the process once on a spartanIIE and gave no
problems and the first time it worked on the virtexII but when we used the
same method again a few hours later it did nothing, every signal remained
unchanged...


"Paulo Dutra" <paulo@xilinx.com> wrote in message
news:3FB3C5D5.1BB56707@xilinx.com...

I'm guessing this produces a multiple drivers error in synthesis.
Is this what you meant by "How come neither of these methods work???"


Yttrium wrote:

Hey, i have this problem when i want to do the following thing:

I have this serial input (let's call it a) and i want to see the serial
input a through an IO provided on my evaluation board (let's call that
pin
atest) and i did it like this

entity testmodule is
port(
a, clk: in std_logic;
b, atest: out std_logic
);
end testmodule;

architecture Behavioral of testmodule is

begin

-- the rest of the program to get a =>b

--with this process i want to feed the input a to and debug output atest
which it clocked on the clk (which is a lot
--faster than the serial clock so there should be no problem there
process(clk)
begin
if (clk'event and clk='1') then
atest<=a;
end if;
end process;

--OR can i just write the following;
atest<=a;

end Behavioral;

so i used a process to bring a => atest as a first method and then
atest<=a
as a second method.
How come neither of these methods work??? did i miss something?

thanx in advance;

Yttrium

--
/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
\ \ ` Xilinx hotline@xilinx.com
/ / 2100 Logic Drive http://www.xilinx.com
\_\/.\ San Jose, California 95124-3450 USA