VirtexII-DPRAM not used

[srini]

Hi,
I generated a DPRAM using Xilinx Coregen and used the <dpram>.v for
synthesis using Synplify Pro -v 8.4. In the <dpram>.v file, I have
added the "synthesis syn_black_box" directive and in the SCOPE
attributes tab and I have chosen the instantiated object name in the
top module to be inferred as block ram. I dont know whether this the
correct way of using Coregen components in Synplify Pro. Plz let me
know the correct way.
After synthesizing, I took the EDF file and implemented it using Xilinx
PAR. In the FPGA utilization summary report, against DPRAM I am seeing
'0'. Why is it so? What Coregen components should be added to the
Xilinx project?
After synthesis or implementation, can I see a technology or RTL view
(in either Xilinx or Synplify Pro) to make sure that a DPRAM is used in
my design?

Thanks & Regards,
Srini.

 

Hello Srini,

syn_black_box must be used, because Coregen already produced a
pre-compiled/pre-synthezied macro.
Synplify should not think about synthesizing it again. Therefore it is
correct what you do.

After synthesizing, you took the EDIF file of your design. But, this
design has black boxes (holes inside),
so you must also deliver their EDIF files as option to Xilinx tools.
You must tell the location
where Xilinx tools should find the pre-compiled EDIF descriptions of
your black boxes.
Check your options.

You can see RTL/technology view only after Synplify synthesizes a
Verilog code.
You cannot view Xilinx output in Synplify.
I suggest you to use Xilinx layout viewer tools. Trace the signal to
your DPRAM.

Utku.

 

[Mike Treseler]

srini wrote:

I dont know whether this the
correct way of using Coregen components in Synplify Pro. Plz let me
know the correct way.

If you prefer, Synplify can infer the dpram directly from
an HDL code template and handle all the messy details for you.

-- Mike Treseler