virtex4 software reset problem.

[Jasim Khan]

HI


I made a small amendment to a tutorial I found online "http://www.fpgadeveloper.com/2008/02/integrating-vhdl-design-into-peripheral-2.html" (which worked fine), but it is not working as one could expect. Can anyone tell me why?

Please see my C code area with asterisk to find the problem.
I am guessing the problem is with software reset. If yes, How do I fix this?


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity multiplier is
port(
clk : in std_logic;
rst : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
p : out std_logic_vector(31 downto 0)
);
end multiplier;

architecture IMP of multiplier is

begin
process (clk, rst)
begin
if(rst = '1') then
p <= B"10101010101010101010101010101010";
elsif (clk'event and clk = '1') then
p <= unsigned(a) * unsigned(b);
end if;
end process;
end IMP;






#include "xmk.h"
#include "sys/init.h"
#include "platform.h"
#include "xparameters.h"
#include "xbasic_types.h"
#include "xstatus.h"
#include "testplb_02.h"
#include <stdio.h>

Xuint32 *baseaddr_p = (Xuint32 *)XPAR_TESTPLB_02_0_BASEADDR;

int main()
{
Xuint32 baseaddr;
Xuint32 DataIN = 0;
Xuint32 DataOUT = 0;

init_platform();

// Check that the peripheral exists
XASSERT_NONVOID(baseaddr_p != XNULL);
baseaddr = (Xuint32) baseaddr_p;

TESTPLB_02_mReset(baseaddr);

// Reset read and write packet FIFOs to initial state
TESTPLB_02_mResetWriteFIFO(baseaddr);
TESTPLB_02_mResetReadFIFO(baseaddr);


DataOUT = TESTPLB_02_mReadFromFIFO(baseaddr, 0);
//**************************************
// DataOUT is 0, where as it should be B"101010...." as in the reset.
// So in a nut shell, FPGA doesnot reset correctly.
// Rest of the code works fine.
//***************************************
DataIN = 131074; //2*2
TESTPLB_02_mWriteToFIFO(baseaddr, 0, DataIN);

DataOUT = TESTPLB_02_mReadFromFIFO(baseaddr, 0);

if(DataOUT != 4)
{
DataOUT = DataOUT;
}

DataIN = 327685; //5*5
TESTPLB_02_mWriteToFIFO(baseaddr, 0, DataIN);

DataOUT = TESTPLB_02_mReadFromFIFO(baseaddr, 0);

if(DataOUT != 25)
{
DataOUT = DataOUT;
}

DataIN = 524296; //8*8
TESTPLB_02_mWriteToFIFO(baseaddr, 0, DataIN);

DataOUT = TESTPLB_02_mReadFromFIFO(baseaddr, 0);

if(DataOUT != 64)
{
DataOUT = DataOUT;
}

DataIN = 524295; //7*8
TESTPLB_02_mWriteToFIFO(baseaddr, 0, DataIN);

DataOUT = TESTPLB_02_mReadFromFIFO(baseaddr, 0);

if(DataOUT != 56)
{
DataOUT = DataOUT;
}


// Stay in an infinite loop
while(1){
}


// Reset the read and write FIFOs
TESTPLB_02_mResetWriteFIFO(baseaddr);
TESTPLB_02_mResetReadFIFO(baseaddr);


return 0;
}