Virtex4: I don't understand their thinking....

[Brannon King]

So after looking at the Virtex4 line of devices and their associated
features
(http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v4_asmbl), I'm a
little miffed at their chip resource allocation.

First of all, suppose I'm planning on filling an FPGA full of logic. I'm
probably going to run the majority of that logic in the same clock domain so
I don't need a whole lot of DCMs. However, I do need some way to get my data
to/from the chip. What's up with zero transceivers on the "logic platform"?
The same can be asked of the "signal processing platform". I was so looking
forward to getting away from the old parallel I/O issues, and if I'm going
to have to deal with that, maybe we better leave those DCMs on there. It
wouldn't take very many transceivers to alleviate the issue.

Second, what about those of us who build and prototype digital bus
controllers, routers, and similar applications. In that situation I'm
looking for an FPGA with lots of memory, lots of transceivers, lots of DCMs,
a fair amount of logic, and not much else. DSP and Processors don't really
help me in that type of application, yet to get what I need I will end up
spending the extra money for the FX chip.

 

[Peter Alfke]

Brannon, wait until Xilinx releases the real details, and I am sure you
will like them.
There is a lot of flexibility in the I/O on all Virtex-4 families.
As to the large number of global clock lines and DCMs, Xilinx must to
cater to a wide range of customers, and some need them. If you need
less, you can always leave them unused, but if you need more than are
available, you (and we) would have a serious problem.

DSP circuits can be used for many other functions than DSP.
Be patient...
Peter Alfke


Brannon King wrote:

So after looking at the Virtex4 line of devices and their associated
features
(http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v4_asmbl), I'm a
little miffed at their chip resource allocation.

First of all, suppose I'm planning on filling an FPGA full of logic. I'm
probably going to run the majority of that logic in the same clock domain so
I don't need a whole lot of DCMs. However, I do need some way to get my data
to/from the chip. What's up with zero transceivers on the "logic platform"?
The same can be asked of the "signal processing platform". I was so looking
forward to getting away from the old parallel I/O issues, and if I'm going
to have to deal with that, maybe we better leave those DCMs on there. It
wouldn't take very many transceivers to alleviate the issue.

Second, what about those of us who build and prototype digital bus
controllers, routers, and similar applications. In that situation I'm
looking for an FPGA with lots of memory, lots of transceivers, lots of DCMs,
a fair amount of logic, and not much else. DSP and Processors don't really
help me in that type of application, yet to get what I need I will end up
spending the extra money for the FX chip.

 

[Symon]

I bet the answer you get from Xilinx will be along the lines of "we analysed
X number of designs from our customer base and found these three to be the
best fit (to maximise our profits)". They won't actually say the bit in
parentheses, but that's what they're in business for. Fair enough.
I guess the 'new' architecture makes it somewhat easier to add further
variants. After all, they've only used three letters (LSF) so far, that
leaves space for 23 more mixes! ;-)
I'm excited that the block structure will finally make partial
reconfiguration a reality.
cheers, Syms.

 

[Austin Lesea]

Brannon,

Well, one can either say the glass is half full, or half empty.

In an extensive survey of customers, we organized the Virtex 4 family
into the LX, FX, and SX.

The idea was pretty simple: we have a lot of customers today who do not
use the MGTs, and want more logic for less cost(LX). They feel that
they could have a lower cost solution if we did not put MGTs and 405PPCs
in the chip (which they end up not using).

Then there are those that like the MGTs. They have found that the MGTs
go well with the 405PPCs, and those that like the PPCs often find use
for the MGTs. The logic and BRAM has to be sufficient to balance these
applications out, so the FX family is targeted for those folks.

Then there are the DSP folks, (who quite frankly are happy with no one
and nothing!). They want humongous amounts of DSP specific
functionality (logic? who needs logic?). The SX family is intended for
them. If we wished to add the MGTs to the SX family, then we have to
ask, do they also need 405PPCs (as the two go together very well in
talking to users). Maybe they do? Maybe they should?

Three major families.

If there is a significant demand for a hybrid of the feature sets, well,
talk to us about it. With ASMBL, it can be done without moving heaven
and earth. But remember that we supply a general purpose solution (now
three general purpose solutions) so the chip has to have an almost
universal appeal to a market segment, or it is not worth the effort to
do it.

As for clocks, I am happy to hear you only use one clock, but consensus
is that we need to supply more global (and local) clocks with increasing
numbers of CLBs to meet our customers' requirements.

Prototyping ASICs is no longer our "big" business. In fact, it has
gotten progressively smaller over the years as ASICs get progressively
more difficult to do at all. We love when people just have to have the
largest parts we make, however.

If the mask for the next ASIC costs $2 million, then the cost (price) of
the FX vs. the LX is not an issue anyway.

Austin

Brannon King wrote:

So after looking at the Virtex4 line of devices and their associated
features
(http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v4_asmbl), I'm a
little miffed at their chip resource allocation.

First of all, suppose I'm planning on filling an FPGA full of logic. I'm
probably going to run the majority of that logic in the same clock domain so
I don't need a whole lot of DCMs. However, I do need some way to get my data
to/from the chip. What's up with zero transceivers on the "logic platform"?
The same can be asked of the "signal processing platform". I was so looking
forward to getting away from the old parallel I/O issues, and if I'm going
to have to deal with that, maybe we better leave those DCMs on there. It
wouldn't take very many transceivers to alleviate the issue.

Second, what about those of us who build and prototype digital bus
controllers, routers, and similar applications. In that situation I'm
looking for an FPGA with lots of memory, lots of transceivers, lots of DCMs,
a fair amount of logic, and not much else. DSP and Processors don't really
help me in that type of application, yet to get what I need I will end up
spending the extra money for the FX chip.

 

[Phil Hays]

"Brannon King" wrote:

So after looking at the Virtex4 line of devices and their associated
features
(http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v4_asmbl), I'm a
little miffed at their chip resource allocation.

Oh, everyone is miffed at chip resource allocation. Almost always.
But for different reasons. Just for a second, think about this from
Xilinx's point of view:

They can't make lots of different chips. Each different type adds to
the development costs, support costs, inventory costs and sales costs.

Some of their customers need lots of (Pick one: RAM, IOs, DCMs,
processors, transceivers, multipliers, LUTS and FFs). Many other
customers need less or could even care less. For example, I've never
worked on a chip that had a reasonable use for a multiplier since the
XC4000 days, when there wasn't any multipliers!

So the chips Xilinx make must be compromises. What I see in the
Virtex4 line is the following:

1) The logic platform is reasonable for things that are basically data
movers/processors with RAM buffers. Yes, transceivers might be useful
for some, but parallel IO isn't dead yet, and will not be dead as long
as DDR SDRAM is the commodity memory technology. Probably not enough
internal memory, but I'm sure there are other opinions!

2) The DSP platform is probably reasonable for DSP. Perhaps someone
more versed in the DSP would could comment?

3) The full-featured platform should cover most other uses, but expect
to pay for features you don't need.

Now, did Xilinx miss any large volume uses of FPGAs? I don't think
so. Sure, a prototype router might require no hard processor, no
multipliers and other DSP support, and the designer will need to buy
the FX chip with these features, but how many of these are going to be
built?

YMMV, SRA, SDD, OMNHO, ...


--
Phil Hays
Phil_hays at posting domain should work for email

 

[Austin Lesea]

Symon,

Ha ha ha.

That was really funny (really, it was). Almost quoted me chapter and verse.

And I would hope it is OK with everyone that Xilinx continues to make
money so that we can enable all of you to do likewise.

Glad you are not puzzled by any of this.

Austin

Symon wrote:

I bet the answer you get from Xilinx will be along the lines of "we analysed
X number of designs from our customer base and found these three to be the
best fit (to maximise our profits)". They won't actually say the bit in
parentheses, but that's what they're in business for. Fair enough.
I guess the 'new' architecture makes it somewhat easier to add further
variants. After all, they've only used three letters (LSF) so far, that
leaves space for 23 more mixes! ;-)
I'm excited that the block structure will finally make partial
reconfiguration a reality.
cheers, Syms.

 

[Stifler]

Hey,

Why so much negativity on this board regarding V4 already? It's the
most kick-ass and awesome FPGA ever made. How bout some kudos and a
big thanks to Xilinx for stepping up to the plate and hitting one out
of the park?

If you think the parts are not planned right or no thinking was put
into it you are on a different planet. The people with the most desire
for the right features determined the results. I really don't think
Xilinx told their customers what they need. So I would humbly submit
to you that if you don't understand the thinking, then you don't
understand the market.

Anyway, let's get a bit excited on this board about the most
significant advancement in FPGA technology in several years. It will
completely blow Stratix II and anything else out of the water in every
regard. Great thinking and innovation seem to be poured into V4.

500 MHz all over the place.
3 versions, Everything, logic, DSP
PPC 405
600 to 11 Gbps I/O
1 Gbps I/O on every pin

Sounds pretty spectacular to me. So get a bit excited and have some
positive thinking out there. V4 SX, LX, and FX are going to be the
standard in 90 nm FPGA technology.

Yeah!


"Brannon King" <bking@starbridgesystems.com> wrote in message news:<ca9v66$m5@dispatch.concentric.net>...

So after looking at the Virtex4 line of devices and their associated
features
(http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v4_asmbl), I'm a
little miffed at their chip resource allocation.

First of all, suppose I'm planning on filling an FPGA full of logic. I'm
probably going to run the majority of that logic in the same clock domain so
I don't need a whole lot of DCMs. However, I do need some way to get my data
to/from the chip. What's up with zero transceivers on the "logic platform"?
The same can be asked of the "signal processing platform". I was so looking
forward to getting away from the old parallel I/O issues, and if I'm going
to have to deal with that, maybe we better leave those DCMs on there. It
wouldn't take very many transceivers to alleviate the issue.

Second, what about those of us who build and prototype digital bus
controllers, routers, and similar applications. In that situation I'm
looking for an FPGA with lots of memory, lots of transceivers, lots of DCMs,
a fair amount of logic, and not much else. DSP and Processors don't really
help me in that type of application, yet to get what I need I will end up
spending the extra money for the FX chip.

 

[Adam Megacz]

Can you point me to some technical data on the enhanced partial
reconfig capabilities? I'm very interested in this area and I can't
seem to find anything on Xilinx's site that wasn't written by somebody
from the marketing department.

- a

"Symon" <symon_brewer@hotmail.com> writes:

I bet the answer you get from Xilinx will be along the lines of "we analysed
X number of designs from our customer base and found these three to be the
best fit (to maximise our profits)". They won't actually say the bit in
parentheses, but that's what they're in business for. Fair enough.
I guess the 'new' architecture makes it somewhat easier to add further
variants. After all, they've only used three letters (LSF) so far, that
leaves space for 23 more mixes! ;-)
I'm excited that the block structure will finally make partial
reconfiguration a reality.
cheers, Syms.

--
"The first time I read this book I felt what I could only explain as a
great disturbance in the Force: it was as if a billion washing
machinces all became unbalanced at once and were suddenly silenced."

-- anonymous book reviewer on Amazon.com

 

[John_H]

"Stifler" <seannstifler69@hotmail.com> wrote in message
news:bf780a06.0406102214.3bc26509@posting.google.com...

Hey,

Why so much negativity on this board regarding V4 already? It's the
most kick-ass and awesome FPGA ever made. How bout some kudos and a
big thanks to Xilinx for stepping up to the plate and hitting one out
of the park?

Has it been made yet? I was real happy to see the announcement but a bit
disappointed that it didn't come with some data sheets for a good
architectural description with all the minutia about resources available in
the planned parts. I'm okay with not having working silicon for a short
while but I think some of the backlash on this board was because of the
insensitive tease. Bait the engineers with something that looks very good
but don't give them any real meat. I'm looking forward to further news.

If you think the parts are not planned right or no thinking was put
into it you are on a different planet. The people with the most desire
for the right features determined the results. I really don't think
Xilinx told their customers what they need. So I would humbly submit
to you that if you don't understand the thinking, then you don't
understand the market.

Anyway, let's get a bit excited on this board about the most
significant advancement in FPGA technology in several years. It will
completely blow Stratix II and anything else out of the water in every
regard. Great thinking and innovation seem to be poured into V4.

You may be overstating a bit to suggest this is "the most significant
advancement" since the features are almost everything we've already seen.
The PPC, the MGT, the CLB structure (I believe) are all pretty much the
same. The evolutionary features that are attractive include the enhanced
DSP elements including hardware divide and the no-overhead FIFO mode for the
BlockRAMs. Neat stuff, but it doesn't come across as a revolutionary
product. Evolutionary is fine.

Didn't Stratix-II come out with a "revolutionary" change to the LUT
structures to allow interesting input configurations such as independent
3-bit and 5-bit input functions without chewing up other resources? A
little flexibility is a good thing. Don't get me wrong - I like the LUTs we
get from Xilinx thanks to the memory and SRL capabilities; I've used them
virtually unchanged for years and years.

500 MHz all over the place.
3 versions, Everything, logic, DSP
PPC 405
600 to 11 Gbps I/O
1 Gbps I/O on every pin

A nice feature set, indeed.

Sounds pretty spectacular to me. So get a bit excited and have some
positive thinking out there. V4 SX, LX, and FX are going to be the
standard in 90 nm FPGA technology.

Yeah!

I'm hoping Xilinx continues to deliver the price/performance advantages
we've come to enjoy.
Looking forward to it!

 

[rickman]

Symon wrote:

I'm excited that the block structure will finally make partial
reconfiguration a reality.

I missed something. I don't see anything that talks about partial
reconfiguration and what I do see indicates these parts are still
designed around columns.

I am still waiting for modular configuration support for Spartan 3. I
was told over six months ago that they had just a couple of issues that
needed to be addressed before they could provide this and that Xilinx
was commited to providing this feature.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Symon]

Adam,
I don't know any technical details, but it struck me that the block
structure is ideally suited to partial reconfiguration on a block by block
basis. It's like lots of mini FPGAs on one die, much more than it was
before. I don't believe that Xilinx will pass up this opportunity to tune
the software to allow block by block P&R etc. I envisage an application, a
bit like Ultracontroller, that demonstrates 'partial configuration for
dummies' of a ASBL block with a standardised interface to adjacent blocks.
I'd recommend pestering your FAE, if enough people are interested or, more
importantly, enough people will use this feature, I'm sure the marketing
machine will respond! From my point of view, with an FPGA with as many gates
as these parts will have, I think partial reconfiguration will become the
norm as more and more little ASICs are converted to IP and hoovered up into
the FPGA.
cheers, Syms.

"Adam Megacz" <adam@megacz.com> wrote in message
news:m13c521ot7.fsf@nowhere.com...

Can you point me to some technical data on the enhanced partial
reconfig capabilities? I'm very interested in this area and I can't
seem to find anything on Xilinx's site that wasn't written by somebody
from the marketing department.

- a

 

[Symon]

Rick,
I'm so excited that maybe my grammar got away from me. Try replacing
'excited' with 'optimistic' to get what I meant. The 'new' thing that Xilinx
is pushing is this ASBL block structure. Surely(!?) they've designed these
blocks to be easily individually programmable? Especially as valued
customers like us have been pushing for it for years?
Cheers, Syms.
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:40C9D9F9.E6D04ADB@yahoo.com...

Symon wrote:

I'm excited that the block structure will finally make partial
reconfiguration a reality.

I missed something. I don't see anything that talks about partial
reconfiguration and what I do see indicates these parts are still
designed around columns.

 

[rickman]

I would be willing to bet NOT. I don't see any sign that the ASBL
blocks relate to configuration blocks. Yeah, it would be a great think
if they could do that, but I'm not holding my breath.


Symon wrote:

Rick,
I'm so excited that maybe my grammar got away from me. Try replacing
'excited' with 'optimistic' to get what I meant. The 'new' thing that Xilinx
is pushing is this ASBL block structure. Surely(!?) they've designed these
blocks to be easily individually programmable? Especially as valued
customers like us have been pushing for it for years?
Cheers, Syms.
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:40C9D9F9.E6D04ADB@yahoo.com...
Symon wrote:

I'm excited that the block structure will finally make partial
reconfiguration a reality.

I missed something. I don't see anything that talks about partial
reconfiguration and what I do see indicates these parts are still
designed around columns.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Simon Peacock]

The real question is not if the support partial reconfiguration ... but you
and how many others want it... there was a partially configurable Xilinx
....once .. many years ago... but it came and went.. this is capitalism not
fantasy money talks the rest walk.
So unless someone is willing to spend $$$ partial reconfiguration is an
electric dream. and if you really need it.. put down 2 devices

Simon


"Symon" <symon_brewer@hotmail.com> wrote in message
news:2iu5tqFqvetqU1@uni-berlin.de...

Rick,
I'm so excited that maybe my grammar got away from me. Try replacing
'excited' with 'optimistic' to get what I meant. The 'new' thing that
Xilinx
is pushing is this ASBL block structure. Surely(!?) they've designed these
blocks to be easily individually programmable? Especially as valued
customers like us have been pushing for it for years?
Cheers, Syms.
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:40C9D9F9.E6D04ADB@yahoo.com...
Symon wrote:

I'm excited that the block structure will finally make partial
reconfiguration a reality.

I missed something. I don't see anything that talks about partial
reconfiguration and what I do see indicates these parts are still
designed around columns.